Flip-Chip Doherty Amplifier Layout for Low Coupling at High Frequency
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Solution Overview
Problem
Conventional Doherty amplifier designs face challenges in semiconductor package design due to signal coupling between carrier and peaking amplifiers, particularly for high-frequency applications, leading to inefficiencies and performance degradation.
Innovation Solution
Implementing transistor amplifiers and passive electrical components in a flip chip configuration, using conductive bumps and multi-layer laminates to eliminate wirebonds, thereby reducing signal coupling and enabling efficient operation at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete devices and components are used in Doherty amplifier package design, then ease of manufacture is improved, but signal coupling between carrier and peaking amplifiers increases causing performance degradation
Solution Approach 1:
The patent merges the carrier amplifier, peaking amplifier, and matching network components into a single integrated semiconductor device. This integration eliminates the discrete components and conductors that caused signal coupling issues, while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Solution Approach 2:
The patent implements a nested structure where the matching network components (inductors, capacitors) are positioned within or adjacent to the amplifier circuits on the same semiconductor substrate. This nesting reduces the physical distance between components, minimizing signal coupling while enabling compact integration.
2Reliability
If discrete devices are maintained at a distance apart, then signal coupling is reduced, but device complexity and package size increase
Solution Approach 1:
The patent combines multiple amplifier paths and matching network components into a single integrated semiconductor device, eliminating the need for separate discrete devices and reducing package complexity while maintaining signal coupling reduction through proper layout design.
Solution Approach 2:
The patent utilizes vertical integration and multi-layer substrate structures to position components in three-dimensional space rather than simply increasing horizontal distance. This allows compact packaging while maintaining electrical isolation between carrier and peaking amplifier paths.
3Ease of manufacture
If discrete devices and conductors are used, then ease of manufacture is improved, but signal loss increases at high frequencies
Solution Approach 1:
The patent integrates all amplifier and matching network components on a single semiconductor substrate, eliminating external conductors and connections that cause signal loss at high frequencies. This integration maintains manufacturing simplicity while dramatically reducing energy loss.
Data Source
AI summary
A power amplifier includes a substrate, first and second transistor amplifiers, and at least one matching circuit. Respective output terminals of the first and second transistor amplifiers are coupled to a combining node, and the matching circuit includes one or more passive electrical components coupled between one of the respective output terminals and the combining node. At least one of the first and second transistor amplifiers or the one or more passive electrical components is mounted on the substrate in a flip chip configuration. The matching circuit may include a shunt inductance that is coupled to the one of the respective drain terminals by a conductive bump. Related devices are also discussed.