Flip-Chip Doherty Amplifier Matching to Reduce Signal Coupling
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Solution Overview
Problem
Conventional Doherty amplifier designs face challenges in achieving high efficiency at back-off power due to signal coupling between carrier and peaking amplifiers, particularly at high frequencies, which complicates semiconductor package design and reduces power handling capability.
Innovation Solution
The design incorporates a substrate with flip chip configurations for transistor amplifiers and passive electrical components, such as shunt inductances provided by integrated passive devices or multi-layer laminates, eliminating wirebonds to minimize signal coupling and optimize phase delay and impedance matching, thereby enhancing power handling and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete devices and components are used in Doherty amplifier package design, then ease of manufacture is improved, but device complexity increases due to multiple distinct components requiring precise positioning
Solution Approach 1:
The patent combines multiple discrete components (transistor die, inductance components, capacitance components) into an integrated circuit structure where these elements are fabricated together on a single substrate. This integration reduces the number of separate parts that need to be manually positioned and assembled, thereby reducing device complexity while maintaining manufacturability through standard IC fabrication processes.
Solution Approach 2:
The integrated circuit substrate serves multiple functions simultaneously: it provides the transistor die for amplification, contains the inductance and capacitance components for impedance matching and phase delay, and acts as the structural platform for interconnections. This multi-functionality eliminates the need for separate discrete components and reduces overall device complexity.
2Object-affected harmful factors
If distinct power transistor die and components are positioned at a distance apart, then signal coupling between carrier and peaking amplifiers is reduced, but area of the device package increases
Solution Approach 1:
The patent employs ground isolation structures and shielding regions between the carrier and peaking amplifier paths that create localized electromagnetic isolation zones. These structures provide targeted signal coupling reduction at critical interfaces without requiring the entire device package to be enlarged, thus maintaining compact dimensions while minimizing harmful signal coupling.
Solution Approach 2:
The patent introduces intermediate isolation structures, such as ground planes and shielding elements, positioned between the carrier and peaking amplifier components. These intermediary elements act as electromagnetic barriers that prevent direct signal coupling while allowing the amplifiers to be positioned closer together, thereby reducing the overall package area.
3Ease of manufacture
If wirebonds are used for connecting components, then ease of manufacture is improved, but signal coupling and phase delay performance deteriorate at high frequencies
Solution Approach 1:
The patent replaces the mechanical wirebond connection system with integrated circuit interconnection methods, such as metal trace patterns and conductive vias fabricated directly on the substrate. This substitution eliminates the mechanical wirebond structure that causes high-frequency signal coupling and phase delay issues, while maintaining ease of manufacture through standard IC fabrication processes that are inherently suited for producing such interconnections.
Data Source
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Figure 3A~3B
AI summary
A power amplifier includes a substrate, first and second transistor amplifiers, and at least one matching circuit. Respective output terminals of the first and second transistor amplifiers are coupled to a combining node, and the matching circuit includes one or more passive electrical components coupled between one of the respective output terminals and the combining node. At least one of the first and second transistor amplifiers or the one or more passive electrical components is mounted on the substrate in a flip chip configuration. The matching circuit may include a shunt inductance that is coupled to the one of the respective drain terminals by a conductive bump. Related devices are also discussed.