Lead Frame Flip-Chip Package With Dummy Chip Heat Dissipation

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Solution Overview

Problem

Existing package structures with lead frame architectures face challenges in heat dissipation due to limited bump placement, poor thermal conductivity of non-conductive adhesives, and issues with electrostatic discharge (ESD) when silicon surfaces are exposed.

Innovation Solution

A package structure is proposed that includes a lead frame, a first flip-chip, and a first dummy chip affixed on the flip-chip using a non-conductive adhesive layer. The dummy chip serves as additional heat dissipation paths and helps prevent ESD issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If wire bonding is used for IC chip connection, then heat dissipation effectiveness is improved, but electrical resistance increases compared to bumps

Engineering Contradiction:
Improveheat dissipation effectivenessVSAvoidelectrical resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent segments the heat dissipation function from the electrical connection function. The IC chip uses bumps for low-resistance electrical connection to package pins, while separate heat dissipation structures (heat sinks, thermal vias, thermally conductive materials) are introduced to handle heat dissipation, allowing each function to be optimized independently

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary thermal management components between the IC chip and the package exterior. These include thermally conductive adhesive layers, heat dissipation structures, and thermal vias that act as mediators to transfer heat efficiently without interfering with the electrical connection function of the bumps

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If bumps are used for IC chip connection, then electrical resistance is reduced, but heat dissipation effectiveness deteriorates due to limited bump placement quantity

Engineering Contradiction:
Improveelectrical resistanceVSAvoidheat dissipation effectiveness
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent transitions from two-dimensional bump placement on the chip surface to three-dimensional heat dissipation structures extending vertically and laterally. Heat sinks with fins, thermal vias through the package, and layered thermally conductive materials create multiple dimensional pathways for heat dissipation, vastly increasing the heat dissipation surface area beyond what limited bump placement can provide

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If the upper chip in POP configuration is attached via non-conductive adhesive, then integration of IC chips with different functions is enabled, but heat dissipation effectiveness deteriorates due to poor thermal conductivity

Engineering Contradiction:
Improveintegration capabilityVSAvoidheat dissipation effectiveness
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent changes the thermal parameter of the adhesive layer by using thermally conductive adhesive materials with significantly higher thermal conductivity than conventional non-conductive adhesives. This parameter change allows the adhesive to maintain its electrical insulation properties while improving heat dissipation effectiveness across the POP interface

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures at the POP interface, combining thermally conductive adhesive materials with heat dissipation structures and thermal vias. This composite approach enables simultaneous achievement of electrical isolation, mechanical bonding, and enhanced heat dissipation that neither simple adhesives nor single-structure solutions could provide

Inventive Principle:
Principle #40Composite materials

4Temperature

If the silicon surface is exposed by grinding to install heat sink directly, then heat dissipation effectiveness is improved, but ESD issues arise causing charge accumulation and discharge

Engineering Contradiction:
Improveheat dissipation effectivenessVSAvoidelectrostatic discharge
Core Design Contradiction:
TemperatureVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary layer between the exposed silicon surface and the heat sink. This intermediary layer (such as a dielectric coating, adhesive layer, or thermal interface material) maintains thermal contact for heat dissipation while providing electrical isolation to prevent ESD issues and charge accumulation on the exposed silicon surface

Inventive Principle:
Principle #24Intermediary (Mediator)

5Temperature

If the silicon surface is exposed by grinding, then heat dissipation is improved, but package thickness becomes constrained and difficult to adjust

Engineering Contradiction:
Improveheat dissipationVSAvoidpackage thickness
Core Design Contradiction:
TemperatureVSLength of moving object

Solution Approach 1:

The patent makes the package thickness dynamic and adjustable by using compliant thermal interface materials and layered structures. The package can be configured with different thicknesses by adjusting the thickness of adhesive layers, thermal interface materials, and heat dissipation structure heights, allowing adaptation to various mold sizes while maintaining effective heat dissipation through the exposed silicon surface

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The package structure enhances heat dissipation effectiveness by providing additional heat dissipation paths and prevents ESD issues, while also allowing for adjustable package thickness to match various mold sizes.

Implementation Method 1

a first dummy chip affixed on the first flip-chip by a non-conductive adhesive layer to serve as heat dissipation paths for the first flip-chip

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20250201647A1Package structure
Publication Date: 2025.06.19 RICHTEK TECH
  • US20250201647A1 patent drawing
  • US20250201647A1 patent drawing
  • US20250201647A1 patent drawing

AI summary

The present disclosure provides a package structure. The package structure includes a lead frame, a first flip-chip disposed over the lead frame, a first dummy chip affixed on the first flip-chip by a non-conductive adhesive layer to serve as heat dissipation paths for the first flip-chip, and an encapsulant encapsulating the first flip-chip and the first dummy chip.