Flip-Chip Semiconductor Package With Embedded Elongated PCB Traces
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Solution Overview
Problem
The miniaturization and fabrication of semiconductor packages using flip-chip technology is hindered by the need for smaller line widths and pitches in printed circuit boards (PCBs), leading to increased complexity and cost.
Innovation Solution
The use of elongated conductive traces embedded in the PCB, which are narrower than traditional pad structures, allowing for higher I/O density and reduced package size, along with a fabrication method that includes plating and anisotropic etching to control trace width and embed conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional pad structures are used in PCB for flip-chip technology, then connection reliability is ensured, but line widths and pitches must be minimized further leading to increased fabrication complexity and cost
Solution Approach 1:
The invention segments the connection structure into multiple functional layers: elongated conductive traces embedded in the PCB substrate, second conductive structures on the PCB surface, and intermediate conductive structures on the carrier substrate. This segmentation allows each layer to be optimized independently, reducing overall fabrication complexity while maintaining connection reliability.
Solution Approach 2:
The invention introduces a carrier substrate as an intermediary between the PCB and semiconductor device. This intermediate layer with its own conductive structures acts as a buffer, allowing the PCB to use larger, easier-to-fabricate traces while still achieving fine-pitch connections to the device through the carrier substrate's redistribution layers.
2Ease of manufacture
If traditional pad structures are used in PCB for flip-chip technology, then manufacturing process is standardized, but fabrication cost increases due to minimized line widths and pitches
Solution Approach 1:
The invention moves the fine-pitch connection requirement from the PCB layer to the carrier substrate layer. The PCB can use standard, larger-dimension traces embedded in the substrate, while the carrier substrate handles the fine-pitch redistribution, effectively distributing the manufacturing complexity across different dimensional scales.
Solution Approach 2:
The carrier substrate replicates the fine-pitch connection pattern needed for the semiconductor device, allowing the PCB to use coarser, more cost-effective trace dimensions. The carrier substrate acts as a copy or intermediary pattern layer that translates between the PCB's larger pitch and the device's smaller pitch requirements.
3Productivity
If elongated conductive traces are used instead of traditional pads, then I/O density increases and package size reduces, but trace width control precision is required
Solution Approach 1:
The elongated conductive traces are embedded in the PCB substrate during the PCB manufacturing process itself, before the carrier substrate and semiconductor device are assembled. This preliminary action allows the traces to be formed with standard PCB fabrication precision, avoiding the need for ultra-precise trace control in later assembly steps.
Solution Approach 2:
The invention applies different quality requirements to different parts of the connection system: the embedded PCB traces use standard manufacturing precision, while the carrier substrate's intermediate conductive structures provide the fine-pitch precision needed for high I/O density. Each layer has its precision requirements localized to where they are most effectively achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and improves routing ability for high-density semiconductor packages by enabling denser connections and fewer layers in the PCB, thus meeting miniaturization and performance requirements.
Implementation Method 1
plating and anisotropic etching to control trace width and embed conductive structures
Implementation Method 2
plating and anisotropic etching to control trace width and embed conductive structures
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.