Flip-Chip FET Cell Separating Active and Passive Components
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Solution Overview
Problem
Existing FET device chip layouts are inefficient due to the dominance of passive components, leading to wasted space and reduced yield when integrating multiple transistors on a single substrate, particularly at high frequencies, where the integration of matching structures and active components results in parasitics and reduced repeatability.
Innovation Solution
The FET cell is configured using flip-chip technology to separate active components from passive components, with the FET devices mounted on one substrate and the matching structure on another, allowing for a more efficient use of space and improved thermal performance by eliminating the need for substrate thinning and reducing assembly complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive components and active components are integrated on the same substrate, then parasitics are reduced and repeatability is improved, but chip area efficiency deteriorates and manufacturing cost increases
Solution Approach 1:
The invention divides the chip into separate active component die and passive component die, each optimized for their specific function. The active die contains only FET devices on expensive GaAs/GaN substrate, while passive components are placed on a separate, cheaper substrate, resolving the area efficiency problem while maintaining electrical connection through flip-chip bonding.
Solution Approach 2:
The invention extracts passive components from the expensive GaAs/GaN substrate and places them on a separate, lower-cost substrate. This extraction eliminates the waste of expensive substrate material on components that do not require its superior electrical properties, while flip-chip connection maintains the electrical integration benefits.
2Device complexity
If multiple FET devices are manufactured on the same substrate, then circuit integration is improved, but rolled yield deteriorates due to the joint probability of all transistors working
Solution Approach 1:
The invention segments the FET devices into separate dies, where each die contains a manageable number of transistors. This segmentation allows individual die to be tested and sorted, so that only die meeting performance specifications are assembled into the final circuit, eliminating the rolled yield problem while maintaining circuit integration.
3Reliability
If substrate is thinned to enhance thermal performance and prevent higher order mode propagation, then high frequency performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention extracts the high-frequency performance requirements from the substrate thinning process by placing only essential active components on the thinned GaAs/GaN die and connecting them via flip-chip to passive components on a separate substrate. This approach achieves high-frequency performance through optimized interconnect design rather than extensive substrate thinning, reducing manufacturing complexity.
Data Source
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AI summary
The FET cell (200) includes multiple individual transistors and interconnect bumps (211,212,213) that are configured to flip-chip connect to a substrate. The substrate (450) may have the majority of a matching structure for the FET cell. Furthermore, the FET cell may include a stability circuit (220) in communication with the terminals of the individual transistors and further in communication with the interconnect bumps. Additionally, different materials can be used in combination in the FET cell and the separate substrate having the majority of the matching structure. Various materials may be more efficiency used in a FET cell, while other materials are suitable for the separate substrate.