Co-Designing Flip-Chip and Interposer Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional design flows for interposer-based 3D ICs often result in interposer-unfriendly micro bump assignments, leading to increased efforts for inter-chip routing and IR drop issues due to independent flip-chip design, which can cause wire congestion and IR violations.
Innovation Solution
A method for co-designing flip-chips and interposers that involves obtaining information on I/O pads, power pins, and IR constraints to perform bump planning and routing, ensuring uniform power density and minimum conductance, thereby minimizing total wire-length and preventing IR violations through chip-interposer routing and Re-Distribution Layer (RDL) routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flip-chips are designed independently and then placed on interposer, then design flexibility is improved, but micro bump assignment becomes interposer-unfriendly and routing complexity increases
Solution Approach 1:
The patent merges the flip-chip design process with the interposer design process into a unified co-design flow. Instead of independently designing flip-chips and then integrating them, the system simultaneously optimizes both the micro bump assignments on flip-chips and the routing on the interposer, treating them as an integrated design problem that reduces overall routing complexity.
Solution Approach 2:
The patent performs preliminary bump planning and power density analysis during the co-design phase, before final routing is executed. By pre-calculating power density distributions and determining optimal micro bump assignments early in the design process, the system prevents routing conflicts and IR drop issues that would arise from independent design approaches.
2Manufacturing precision
If micro bump assignment is optimized for individual flip-chip, then bump placement precision is improved, but total wire-length on interposer increases
Solution Approach 1:
The patent applies local quality optimization by analyzing power density characteristics at different locations on the interposer and adjusting micro bump assignments accordingly. Instead of using a uniform bump placement strategy, the system tailors bump density and positioning to local power requirements, which minimizes wire-length while maintaining precise bump placement where needed.
Solution Approach 2:
The patent dynamically adjusts micro bump assignment parameters during the co-design process based on interposer routing requirements. By changing bump placement parameters in response to overall system optimization goals, the system reduces total wire-length while maintaining adequate bump placement precision for functional requirements.
3Reliability
If power bumps are increased to reduce IR drop, then power delivery reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements feedback mechanisms that analyze power density distributions and IR drop risks during the co-design process. The system uses this feedback information to determine the minimum necessary number of power bumps required for reliable power delivery, avoiding both over-provisioning (which increases complexity) and under-provisioning (which compromises reliability).
Solution Approach 2:
The patent applies partial action by providing power bumps only where and where needed based on local power density analysis. Instead of uniformly increasing power bumps across the entire device, the system strategically places power bumps in regions with high power demand, achieving adequate power delivery reliability without unnecessarily increasing overall device complexity.
Data Source
AI summary
A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.