Flip-Chip Interposer Layout for Dense Wirebonded Assemblies
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Solution Overview
Problem
Existing wirebonded chip-and-wire circuit assemblies face limitations in interconnection density and footprint due to the requirement for interconnection points only at the die perimeter, and upgrading to flip-chip dies is costly and incompatible with existing designs.
Innovation Solution
An interposer is used to adapt flip-chip dies for direct wirebond interconnection with surrounding wirebond dies, incorporating a flip-chip interconnection array on an insulating substrate with compatible solder bump connection pads and wirebond pads, allowing for increased interconnections and integration with a motherboard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wirebonding is used to connect dies, then interconnection points can be located at the die perimeter, but the number of connection points is limited and the footprint is enlarged
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the die and the package substrate. The interposer contains an array of vias and conductive traces that route signals from pad sites distributed across the die surface (not just the perimeter) to the package substrate, enabling increased connection density without enlarging the die footprint.
2Quantity of substance
If flip-chip dies are used to increase interconnection density, then more connection points are available, but manufacturing costs increase and compatibility with existing wirebonded designs is lost
Solution Approach 1:
The interposer serves as a mediator that allows flip-chip dies to be integrated into existing wirebonded circuit assemblies. The interposer provides wirebond pad sites that are compatible with traditional wirebonding processes, while simultaneously supporting flip-chip die attachment through its array of vias and conductive traces, thus enabling hybrid assembly approaches.
Solution Approach 2:
The interposer is designed with multi-functionality to support both wirebonding and flip-chip die attachment methods. It contains both wirebond pad sites for traditional wirebond connections and an array of vias for flip-chip die interconnections, making it universally compatible with different die attachment technologies and reducing the need for complete design redesigns.
3Ease of manufacture
If interconnection points are located only at the die perimeter, then wirebonding is simplified, but the maximum number of interconnections is limited
Solution Approach 1:
The patent transitions from one-dimensional perimeter-based interconnection to two-dimensional surface-distributed pad sites. The interposer contains an array of vias and conductive traces that route signals from pad sites located anywhere on the die surface (not just the perimeter) to the package substrate, effectively utilizing the two-dimensional die surface area for interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interposer enhances interconnection density and high-frequency performance while minimizing footprint, reducing manufacturing costs by integrating flip-chip dies into existing wirebonded assemblies without redesigning the entire circuit.
Implementation Method 1
heating the flip-chip and interposer interconnection arrays of solder bump connection pads until they melt and form interconnections with each other
Implementation Method 2
forming a wirebond connection between the wirebond pad of the interposer and the wirebond interconnection point of the wirebond die by welding a first end of a wirebond to the wirebond interconnection point of the wirebond die and welding a second end of the wirebond to the wirebond pad of the interposer
Data Source
AI summary
An interposer that enables implementation of a flip-chip die in a wirebonded chip-and-wire circuit assembly includes an insulating substrate having a solder bump pad array on its upper surface that is compatible with the solder bump array of a flip-chip die. Wirebond pads provided along upper edges of the substrate are interconnected to at least some of the solder bump pads. Bonding the interposer to the circuit assembly housing floor, or through an opening to an underlying motherboard, places the wirebond pads proximate attachment points of adjacent wirebond dies, enabling wirebonding therebetween. Attachment pads on the interposer lower surface, in combination with interconnecting traces and vias, can enable connection directly through the housing opening to the underlying motherboard. Support components can be included within an edge cavity created beneath an overhang of a multi-layer substrate. A heat absorbing plate can be attached to the top of the flip-chip die.