Flip-Chip Leadframe Interconnect With Vertical Protrusions for High Current
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Solution Overview
Problem
Traditional wire bonding methods for semiconductor power devices face limitations in handling high current densities, leading to increased complexity, cost, and reliability issues, while clip bonding introduces manufacturing challenges and errors.
Innovation Solution
A flip-chip packaging solution using a leadframe with vertical protrusions and a conductive film, allowing for parallel interconnect formation through sputtering or plating, eliminating sequential clip bonding and soldering processes, and enabling efficient thermal dissipation with a double-sided cooled configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clip bonding is used to handle high current densities, then electrical performance and heat distribution are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the bonding process entirely by using pre-formed metal clips that are mechanically attached to the semiconductor die and leadframe. This eliminates the complex multi-step clip bonding process (solder application, pick-and-place, reflow, flux cleaning, inspection) while maintaining the electrical performance benefits of metal-to-metal contact for high current density applications.
Solution Approach 2:
The metal clips are pre-formed and pre-positioned on the leadframe before the semiconductor die is mounted. This preliminary preparation of interconnect structures simplifies the overall manufacturing process by eliminating the need for complex real-time bonding operations during assembly.
2Reliability
If clip bonding is used to handle high current densities, then electrical performance and heat distribution are improved, but manufacturing time and cost increase
Solution Approach 1:
By removing the multi-step clip bonding process entirely and replacing it with simple mechanical attachment of pre-formed clips, the manufacturing time is dramatically reduced. The complex sequence of solder application, pick-and-place, reflow heating, flux cleaning, and quality inspection is replaced with a single straightforward mounting operation.
Solution Approach 2:
The patent uses simple, inexpensive metal clips that can be mass-produced and pre-positioned. These clips serve as temporary mechanical interconnects during assembly and provide permanent electrical connection, replacing expensive and time-consuming bonding processes.
3Ease of manufacture
If traditional wire bonding is used, then manufacturing process is simpler, but ability to handle high current densities is limited
Solution Approach 1:
The patent merges the advantages of wire bonding (manufacturing simplicity) with the advantages of clip bonding (high current density capability). The metal clips provide wide contact areas for high current density handling while the overall assembly process remains simple and straightforward, avoiding the complexity of traditional wire bonding operations.
Solution Approach 2:
The invention changes the fundamental parameter of interconnect geometry from thin wire (wire bonding) to wide metal clips with large contact areas. This parameter change enables high current density handling while maintaining manufacturing simplicity through mechanical attachment rather than complex wire manipulation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and enhances reliability by providing superior thermal dissipation and electrical performance, suitable for high-power semiconductor devices.
Implementation Method 1
The conductive film may be a sputtered or plated interconnect film forming a lateral electrical contact on the top side of the semiconductor device
Implementation Method 2
The conductive film may be a sputtered or plated interconnect film forming a lateral electrical contact on the top side of the semiconductor device
Data Source
Figure 1a~1b
Figure 1c~2
Figure 3a~3b
AI summary
A semiconductor device (100) and manufacturing method thereof are presented. The device has a top side and a bottom side and comprises a leadframe with pads (110A, 112, 114) extending to the bottom side of and exterior to the device. At least one of the pads comprises a leadframe vertical protrusion (110B) extending from the bottom side to the top side. A die (200) is flip-chip arranged in the semiconductor device and comprises terminals (202, 204, 206). At least one of the terminals (202, 204) on the top side of the die and facing the bottom side of the device is electrically connected to a corresponding pad (112, 114). Another one of the terminals (206) on the bottom side of the die faces the top side of the device where a conductive film (102) electrically connects the terminal (206) to the leadframe vertical protrusion (110B) at the top side.