Flip-Chip LED Array Electrode Wiring
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Solution Overview
Problem
Existing light emitting diode (LED) arrays face challenges in using common AC power sources due to high turn-on voltage requirements, leading to increased fabrication costs, volume, and heat generation, as well as reduced light-emitting performance and heat-dissipating efficiency, particularly when using flip-chip type LEDs without a submount substrate.
Innovation Solution
A flip-chip type LED array is developed with upper electrodes made of identical material, including ohmic contact and reflective conductive layers, connected to semiconductor layers to facilitate high-voltage operation without a submount substrate, reducing light loss and improving light extraction efficiency by covering side surfaces and regions between LEDs with a large-area, plate-like upper electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a submount substrate is used for flip-chip type LED arrays, then wiring between electrodes is enabled, but fabrication costs and product thickness increase
Solution Approach 1:
The patent extracts and eliminates the submount substrate from the LED array structure. Instead of using a separate submount substrate for wiring, the invention integrates the wiring function directly into the LED chip structure through self-aligned electrode patterns that enable inter-LED wiring without requiring an additional substrate layer.
Solution Approach 2:
The upper electrode serves multiple functions simultaneously: it acts as both the electrical contact for the LED and as the wiring interconnection to adjacent LEDs. This multi-functional design eliminates the need for separate wiring structures on a submount substrate, reducing both complexity and thickness.
2Ease of manufacture
If wire bonding is used for connecting LEDs in an array, then electrical connection is achieved, but additional molding process is required increasing process complexity
Solution Approach 1:
The patent merges the electrical connection function with the LED chip structure itself. The upper electrode is integrated into the LED chip and directly provides both the electrical contact and the wiring interconnection to adjacent LEDs, eliminating the need for separate wire bonding and molding processes.
Solution Approach 2:
The LED chip structure serves its own wiring needs through the self-aligned upper electrode design. The electrode patterns are automatically positioned to provide both electrical contact and inter-LED wiring, making the structure self-sufficient without requiring external wire bonding or protective molding.
3Ease of manufacture
If lateral type LED chips are used, then array formation is simplified, but light-emitting performance and heat-dissipating performance deteriorate
Solution Approach 1:
The patent employs asymmetric electrode positioning where the upper electrode is strategically placed to optimize both electrical connection and light extraction. The electrode pattern is asymmetrically designed to allow light to escape through the substrate while maintaining effective electrical contact, thus improving light-emitting performance compared to symmetric lateral structures.
Solution Approach 2:
Instead of using conventional lateral-type LED chips where electrodes are on the sides, the patent inverts the structure by using flip-chip type LEDs with electrodes on the bottom surface. This inversion enables better heat dissipation through the substrate and improved light extraction, while the self-aligned upper electrode maintains simplified array formation.
4Ease of manufacture
If multiple discrete processes are used for LED array fabrication, then each process can be optimized, but total processing time and fabrication cost increase
Solution Approach 1:
The patent combines multiple discrete fabrication processes into integrated steps. The self-aligned upper electrode formation enables simultaneous creation of electrical contacts and wiring patterns in a single lithography and deposition sequence, eliminating the need for separate wire bonding, alignment, and molding processes.
Solution Approach 2:
The upper electrode structure is preliminarily designed with self-aligned features that automatically provide both electrical contact and wiring functionality. This preliminary structuring eliminates the need for subsequent alignment and wiring processes, reducing total processing steps and time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for efficient high-voltage operation of LED arrays without a submount substrate, reducing fabrication costs and improving light extraction efficiency by minimizing light loss and heat dissipation issues, while simplifying the manufacturing process and enabling direct mounting on printed circuit boards.
Implementation Method 1
a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes
Implementation Method 2
upper electrodes made of identical material, including ohmic contact and reflective conductive layers
Data Source
AI summary
Disclosed are a light emitting diode array on a wafer level and a method of forming the same. The light emitting diode array includes a growth substrate; a plurality of light emitting diodes arranged on the substrate, wherein each of the plurality of light emitting diodes has a first semiconductor layer, an active layer and a second semiconductor layer; and a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of an identical material, wherein each of the plurality of upper electrodes is electrically connected to the first semiconductor layer of a respective one of the light emitting diodes. At least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent one of the light emitting diodes, and another of the upper electrodes is insulated from the second semiconductor layer of an adjacent one of the light emitting diodes. Accordingly, it is possible to provide a light emitting diode array that can be driven under at a high voltage and simplify a forming process thereof.