Flip Chip Package Layout for Lower Power-Ground Loop Inductance
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Solution Overview
Problem
Existing flip chip semiconductor packages experience high loop inductance between power and ground paths, which adversely affects device performance.
Innovation Solution
A multilayer package substrate is designed with intermixed power and ground post connect locations on the die side surface, using a mesh or comb structure to increase mutual inductance and reduce loop inductance, while maintaining compatibility with existing circuit board designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power and ground post connects are separated in the die mount area, then the package structure is simpler to manufacture, but the loop inductance increases and device performance deteriorates
Solution Approach 1:
The patent merges power and ground post connect locations in an intermixed pattern within the die mount area. This combining of previously separated power and ground connections into a unified intermixed arrangement reduces loop inductance by creating smaller current loops, thereby improving device performance without significantly complicating the manufacturing process.
2Reliability
If power and ground post connect locations are intermixed in the die mount area, then loop inductance is reduced and device performance is improved, but the package design becomes more complex
Solution Approach 1:
The patent segments the die mount area into multiple discrete post connect locations that are intermixed in a systematic pattern. This segmentation allows power and ground connections to be distributed throughout the mount area in a controlled manner, reducing loop inductance while maintaining a manageable design complexity through regular spacing and patterning.
Solution Approach 2:
The patent applies local quality by creating regions of intermixed power and ground post connects specifically within the die mount area, while other areas of the package substrate maintain their traditional designs. This localized approach to intermixing concentrates the inductance reduction benefit where it is most needed without requiring complex changes throughout the entire package structure.
3Ease of manufacture
If post connects are arranged in traditional separate power and ground areas, then the manufacturing process is simpler, but the current carrying capacity and electrical connectivity are insufficient
Solution Approach 1:
The patent combines power and ground post connect locations into an intermixed arrangement that increases the density of conductive paths. This merging creates multiple parallel current paths between power and ground, thereby increasing the overall current carrying capacity of the package while still using standard manufacturing processes for forming the post connects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces loop inductance, enhancing the performance of packaged semiconductor devices by improving electrical connectivity and current carrying capacity.
Implementation Method 1
solder joints between the post connects and the post connect locations
Data Source
AI summary
In a described example, an apparatus includes: a multilayer package substrate including a die mount area on a die side surface and comprising power pads and ground pads on an opposing board side surface, the multilayer package substrate including post connect locations on the die side surface for receiving power post connects and for receiving ground post connects for a flip chip mounted semiconductor device, the power post connect locations and the ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area; and a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device mounted to the die side surface of the multilayer package substrate by solder joints between the post connects and the post connect locations.