Variable-Thickness Flip-Chip Assembly for Low-k Crack Reduction
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Solution Overview
Problem
Low-k dielectrics in semiconductor manufacturing are prone to cracking due to mechanical stresses during packaging operations, such as reflow soldering and chip pick-up, leading to reduced manufacturing yield.
Innovation Solution
A semiconductor chip with a non-uniform thickness profile, where the corner portions are thinner than the middle portions, alleviating stress-related integrity issues during these operations, thereby reducing the likelihood of low-k dielectric cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor chip has uniform thickness, then the chip structure is simple to manufacture, but the low-k dielectric layers crack during packaging operations due to mechanical stresses
Solution Approach 1:
The patent applies local quality by creating a non-uniform thickness profile where different regions of the semiconductor chip have different thicknesses. Specifically, the chip is thinner at the corners and thicker in the middle portions, allowing each region to be optimized for its specific stress conditions during packaging operations. This local variation in thickness prevents cracking in low-k dielectric layers while maintaining manufacturability.
Solution Approach 2:
The patent changes the physical parameter of chip thickness from a uniform value to a variable value across different regions. By modifying the thickness parameter locally (thinner at corners, thicker in middle), the chip can better withstand the varying mechanical stresses encountered during packaging operations, thereby preventing dielectric cracking without significantly complicating the manufacturing process.
2Strength
If the semiconductor chip is thicker in the middle, then structural support during pick-up is improved, but stress during solder reflow increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform thickness profile where different regions of the semiconductor chip have different thicknesses. Specifically, the chip is thinner at the corners and thicker in the middle portions, allowing each region to be optimized for its specific stress conditions during packaging operations. This local variation in thickness prevents cracking in low-k dielectric layers while maintaining manufacturability.
Solution Approach 2:
The patent applies asymmetry by creating an asymmetric thickness distribution across the chip, with thinner regions at the corners and thicker regions in the middle. This asymmetric profile is specifically designed to address the different stress conditions at different locations during packaging operations, allowing the chip to better withstand both solder reflow and pick-up stresses simultaneously.
Data Source
AI summary
Approaches directed at increasing the production yield of integrated circuits including layers of low-k dielectrics. One example provides a flip-chip assembly including a semiconductor chip attached to a substrate using pillars or bumps. The semiconductor chip has a thickness profile such that the chip is thinner near the corners than in middle portions. The thinner corner portions beneficially alleviate chip-integrity issues related to the stresses generated during the solder reflow operation while the thicker middle portions beneficially alleviate chip-integrity issues related to the stresses generated during the chip or die pick-up operation. Due to the alleviation of both types of chip-integrity issues, the number of instances in which the low-k dielectrics crack during the corresponding assembly operations is significantly reduced, thereby beneficially increasing the manufacturing yield.