Flip-Chip Bonded Memory Logic Module
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Solution Overview
Problem
As 3D memory structures with increasing memory layers face challenges in positioning logic circuits beneath the memory cell structure, and the heat optimization for memory cell formation can adversely affect logic circuit operation, existing technologies struggle to efficiently integrate memory and logic circuits in high-capacity storage devices.
Innovation Solution
The solution involves forming an integrated memory module with separate semiconductor dies for memory cell arrays and logic circuits, where the memory cell array is fabricated on one die and the logic circuit on another, allowing for customized and optimized fabrication processes for each component, and the two dies are flip-chip bonded with specific bond pad sizes and pitches to manage electrical connections effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the logic circuit is positioned beneath the 3D memory cell structure to meet high-capacity storage demands, then memory capacity increases, but positioning and integration difficulty increases
Solution Approach 1:
The patent divides the semiconductor device into separate components: a first semiconductor die containing the 3D memory cell structure and a second semiconductor die containing the logic circuit. This segmentation allows each component to be optimized and fabricated independently, then bonded together, resolving the positioning and integration difficulty while maintaining high memory capacity
Solution Approach 2:
Instead of positioning the logic circuit beneath the memory cell structure in the vertical dimension, the patent transitions to a horizontal arrangement by bonding separate semiconductor dies together. This dimensional change simplifies the integration process while achieving the same functional goal of high-capacity storage with integrated logic control
2Manufacturing precision
If heat annealing is applied to optimize memory cell structure formation, then memory cell quality improves, but logic circuit operation is adversely affected
Solution Approach 1:
By separating the memory cell structure and logic circuit onto different semiconductor dies, the patent enables independent fabrication and heat treatment processes. The memory-containing die can undergo heat annealing to optimize memory cell formation without exposing the logic circuit to damaging temperatures, thus resolving the contradiction between manufacturing precision and reliability
Solution Approach 2:
The patent applies different fabrication conditions to different parts of the system: the first semiconductor die containing memory cells receives heat annealing treatment optimized for memory formation, while the second semiconductor die containing the logic circuit is processed under conditions suitable for logic circuit integrity. This localized quality approach allows each component to be optimized without compromising the other
3Ease of manufacture
If separate semiconductor dies are used for memory and logic circuits, then fabrication process optimization for each component improves, but device complexity increases
Solution Approach 1:
The patent employs segmentation by using separate semiconductor dies for memory and logic circuits, allowing each to be fabricated with optimized processes tailored to its specific requirements. The bonding interface between dies is designed with standardized bond pads and interconnect structures that simplify the integration process, offsetting the increased device complexity through modular design
Solution Approach 2:
The patent implements universal bonding interfaces with standardized bond pad configurations that can accommodate different memory and logic circuit designs. This multi-functionality allows the same bonding process and interconnect structure to work across various device configurations, reducing the complexity increase that would otherwise result from custom integration solutions
Data Source
AI summary
A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.