Semiconductor Flip-Chip Metal Layer Undercutting Prevention

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Solution Overview

Problem

The existing methods for fabricating flip-chip type semiconductor packages face challenges in maintaining alignment accuracy and reliability due to isotropic etching processes, which can lead to undercutting of metal layers and insufficient support for conductive pillars, affecting the reliability of the conductive bumps.

Innovation Solution

A semiconductor fabrication method involving the formation of a first metal layer, a dielectric layer, and a second metal layer, where the first metal layer is larger than the conductive pillar, and the second metal layer is partially removed, ensuring the first metal layer remains covered by the dielectric layer during etching, thereby preventing undercutting and providing adequate support for the conductive pillar.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an isotropic etching process is used to remove the copper layer and titanium layer, then the etching process is simple and efficient, but undercutting of the titanium layer occurs resulting in insufficient support for the copper pillar

Engineering Contradiction:
Improveetching efficiencyVSAvoidvertical profile precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the metal structure into two distinct layers: a first metal layer (titanium) and a second metal layer (copper). The titanium layer is patterned to extend beyond the copper layer boundaries, creating an overlapping structure. This segmentation allows the copper layer to be etched away while the titanium layer remains as an underlying support structure, preventing undercutting and maintaining structural integrity during the etching process.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If the copper layer is completely removed by etching to expose the electrode pad, then the electrode pad is accessible for connection, but the support structure becomes insufficient reducing reliability

Engineering Contradiction:
Improveelectrode pad accessibilityVSAvoidconductive bump reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent performs preliminary action by patterning the titanium layer to extend beyond the copper layer boundaries before the copper etching process. This pre-established overlapping structure ensures that when the copper layer is completely removed to expose the electrode pad, the titanium layer remains as a supporting framework. This preliminary structural preparation maintains both electrode pad accessibility and structural reliability simultaneously.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8866293B2Semiconductor structure and fabrication method thereof
Publication Date: 2014.10.21 SILICONWARE PRECISION IND CO LTD
  • US8866293B2 patent drawing
  • US8866293B2 patent drawing
  • US8866293B2 patent drawing

AI summary

A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.