Flip-Chip-On-Leadframe Package Without Wafer Bumping
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Solution Overview
Problem
Conventional Flip-Chip-On-Leadframe (FCOL) techniques require wafer bumping, which increases costs and delays in the semiconductor package assembly process and limits the current-carrying capacity of bumps.
Innovation Solution
A method that eliminates wafer bumping by placing conductive material, such as solder paste, on a leadframe protrusion, reflowing it to connect with a die active area, and securing the die to the leadframe using an under bump metallization structure and redistribution layer, thereby forming a Flip-Chip-Can-Leadframe (FCOL) package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer bumping is used in FCOL techniques, then die-to-leadframe connection is achieved, but assembly cost and time increase significantly
Solution Approach 1:
The patent extracts and eliminates the wafer bumping step from the FCOL assembly process. Instead of forming bumps on the wafer/die and then attaching to the leadframe, the invention directly attaches the die to the leadframe using solder paste applied to the leadframe protrusions, removing the intermediate bumping operation entirely.
Solution Approach 2:
The patent applies solder paste to the leadframe protrusions before die attachment. This preliminary application of conductive material ensures proper solder joints are formed during the reflow process without requiring subsequent bumping operations, streamlining the assembly sequence.
2Reliability
If conventional wafer bumping is used, then electrical connection is established, but current-carrying capacity of bumps is limited
Solution Approach 1:
The patent enhances the local quality of the connection interface by applying Under Bump Metallization (UBM) structures on the die contact pads and using substantial solder paste volumes on the leadframe protrusions. This creates localized regions of high electrical conductivity and increased current-carrying capacity at the critical die-to-leadframe interface.
Solution Approach 2:
The invention employs composite material structures including UBM layers (typically copper or aluminum with protective overcoats), solder paste (tin-lead or lead-free alloys with flux), and epoxy underfill. These composite materials provide enhanced electrical conductivity, mechanical strength, and thermal management capabilities compared to conventional single-material bumps.
3Reliability
If wafer bumping is performed, then connection structure is formed, but process complexity increases
Solution Approach 1:
The patent merges multiple functions into the die attachment step itself. The solder paste application, die placement, and solder joint formation are combined into a single reflow process, eliminating the need for separate bumping equipment and process steps. This integration simplifies the overall manufacturing workflow and reduces process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces assembly costs and time while enhancing electrical performance and reliability by eliminating the need for wafer bumping and increasing the Under Bump Metallization, allowing for higher current-carrying capacity and efficient semiconductor package assembly.
Implementation Method 1
reflowing the conductive material to raise up the die to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion
Data Source
AI summary
Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.