Flip Chip Semiconductor Package with Metal Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging techniques, such as chip and wire packaging, face challenges with large size, parasitic inductances, and manufacturing complexity, especially when dealing with Gallium arsenide substrates, which are brittle and difficult to work with, and flip chip packaging is not favored due to size issues and material fragility.
Innovation Solution
A near chip scale packaging process using flip chip ball grid array (BGA) devices with a polymer layer and metal deposition to create electrical contacts and electromagnetic shielding, allowing for small, robust, and high-performance RF components with minimal complexity, suitable for high-volume, low-cost production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip and wire packaging is used, then the die can be connected to the carrier, but the package size becomes large and parasitic inductances increase
Solution Approach 1:
The patent inverts the conventional packaging approach by using flip chip technology where the die is mounted upside down with bumps on the bottom surface making direct contact with the carrier. This eliminates the need for bond wires and lead frames extending beyond the die, thereby reducing package size and parasitic inductances while maintaining reliable electrical connections
Solution Approach 2:
The patent extracts and eliminates the bond wires and extended lead frames from the conventional packaging structure. By using direct bump connections between the die and carrier, the unnecessary components that contribute to package size and parasitic inductance are removed, achieving a more compact and electrically superior design
2Reliability
If chip and wire packaging with lead frame is used, then the die can be connected to the carrier, but the keep out area increases
Solution Approach 1:
By inverting the mounting approach with flip chip technology, the die is connected directly to the carrier through bumps on its bottom surface. This eliminates the need for a large lead frame structure that extends beyond the die edges, thereby minimizing the keep out area while ensuring reliable electrical connections
3Reliability
If bond wires are used to connect die to lead frame, then electrical connection is established, but series parasitic inductances are introduced
Solution Approach 1:
The patent extracts and eliminates the bond wires from the electrical connection path. By using direct bump connections between the die and carrier, the inductive effects of bond wires are completely removed, achieving superior RF performance with minimal parasitic inductance while maintaining reliable electrical connectivity
Solution Approach 2:
The patent replaces the mechanical bond wire system with a direct metallurgical bump connection system. This substitution eliminates the loop structure and associated inductance of bond wires, providing a more efficient electrical connection path with lower parasitic inductance for RF applications
4Reliability
If the die is mounted face up with device far from carrier, then the die can be connected, but thermal management becomes difficult
Solution Approach 1:
By inverting the die mounting orientation with flip chip technology, the active devices on the die are positioned close to the carrier which serves as a heat sink. This inversion dramatically improves thermal management by providing a short thermal path from the heat-generating devices to the carrier, while the bumps still provide reliable electrical connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves exceptional RF performance and small size with reduced inductance and improved thermal management, enabling flexible die layout and high signal density, while being cost-effective and suitable for high-volume production, overcoming the limitations of conventional packaging methods.
Implementation Method 1
selectively removing the first polymer layer to provide at least one opening to expose a portion of the die
Implementation Method 2
depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die
Implementation Method 3
including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die
Implementation Method 4
adhering the die to a substrate in a flip chip configuration
Data Source
AI summary
Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.