Flip-Chip Semiconductor Package Thermal Stress Reduction
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Solution Overview
Problem
Conventional semiconductor packages face issues with warpage and cracking due to differences in the coefficient of linear expansion between the substrate and semiconductor chips, leading to reliability concerns, especially with the use of substrates having buildup layers which increase the tendency for cracks and peeling.
Innovation Solution
A flip-chip semiconductor package design incorporating a circuit board with a core layer and buildup layers, utilizing a sealing resin composition with a specific coefficient of linear expansion and glass transition temperature, and a fiber substrate to reduce thermal stress and prevent cracks and peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the core layer thickness is reduced to reduce inductance, then the inductance of the core layer through-holes is reduced, but the coefficient of linear expansion of the substrate increases and the tendency for cracks and peeling increases
Solution Approach 1:
The invention changes the material parameters of the buildup layer by specifying a glass transition temperature of 170°C or more and a coefficient of linear expansion of 25 ppm/°C or less. This allows the core layer to be made thinner for reduced inductance while the high-performance buildup layer compensates for the increased thermal expansion stress, preventing cracks and peeling.
Solution Approach 2:
The invention uses a composite structure combining a thin core layer with a specially formulated buildup layer containing specific resins (cyanate resin, phenol resin, or their combinations) and inorganic fillers. This composite material approach enables the substrate to achieve both low inductance and high reliability by distributing thermal stress across layers with complementary properties.
2Speed
If a substrate having a buildup layer is used to reduce inductance, then the inductance is reduced, but the coefficient of linear expansion increases and cracks and peeling occur more easily
Solution Approach 1:
The invention modifies the buildup layer material parameters by selecting resins with high glass transition temperatures (cyanate resin, phenol resin) and controlling the coefficient of linear expansion to 25 ppm/°C or less. This enables the substrate to support high-speed signal transmission while resisting thermal stress damage through optimized material composition including inorganic fillers.
3Reliability
If the coefficient of linear expansion of the substrate is reduced to prevent cracks and peeling, then reliability is improved, but the inductance increases which is undesirable for high clock frequencies
Solution Approach 1:
The invention applies different material qualities to different layers: the core layer is made thin for low inductance while the buildup layer is formulated with specific resins and fillers to achieve low thermal expansion. This local optimization allows each layer to fulfill its specific function without compromising the other, enabling both high speed and high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses or reduces cracks and peeling, enhancing the reliability of the semiconductor package by maintaining low thermal stress between the semiconductor chip and the circuit board, thereby improving the package's overall reliability.
Implementation Method 1
the cured member having a coefficient of linear expansion at 25 to 75° C. of 15 to 35 ppm/° C., and at least one buildup layer having a glass transition temperature of 170° C. or more and a coefficient of linear expansion at 25 to 75° C. in the planar direction of 25 ppm/° C. or less
Data Source
AI summary
A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.