Flip Chip IC Packaging with Interconnect Recess
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in reducing cost, size, and increasing functionality while maintaining reliability, as existing technologies fail to efficiently configure multi-row quad flat nonleaded packages for flip chip devices with lower height and smaller space requirements.
Innovation Solution
The method involves forming a lead with a passivation layer and an interconnect structure having an inner and outer pad with a recess, directly on the lead top side, mounting an integrated circuit over the inner pad, and encapsulating it, which eliminates lead pullouts, solder creep, and misalignment, and reduces package footprint by using a simpler substrate construction and eliminating solder balls and laminate usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing manufacturing processes are reused, then manufacturing cost is reduced, but package dimensions cannot be reduced
Solution Approach 1:
The patent transitions from traditional planar substrate mounting to vertical stacking architecture, where multiple integrated circuits are stacked in the Z-dimension above the substrate. This dimensional change allows the package to achieve higher integration without increasing the footprint area, resolving the contradiction between using existing manufacturing processes and reducing package dimensions.
Solution Approach 2:
The patent implements a nested structure where integrated circuits are stacked vertically within the package footprint, similar to nested dolls. The first integrated circuit is mounted on the substrate, and subsequent circuits are stacked above it, maximizing space utilization without expanding the overall package area, thus enabling cost-effective manufacturing with reduced dimensions.
2Adaptability or versatility
If integrated circuits are stacked into a single package, then functionality is increased, but lower height and smaller space requirements are not fully addressed
Solution Approach 1:
The patent segments the package into distinct functional layers: substrate with interconnect structure, first integrated circuit, second integrated circuit, and encapsulation. This segmentation allows each component to be optimized independently while maintaining compact overall dimensions, achieving high functionality without excessive height increase.
Solution Approach 2:
The patent employs reflow soldering process parameters to achieve reliable bonding of stacked integrated circuits. By controlling the reflow temperature profile and using lead-free solder alloy composition, the patent achieves strong mechanical and electrical connections while minimizing the vertical space required for the interconnection structure, thus reducing package height.
3Ease of manufacture
If traditional packaging structures are used, then manufacturing is simplified, but reliability issues such as lead pullouts, solder creep, and misalignment occur
Solution Approach 1:
The patent incorporates preliminary alignment features in the interconnect structure design, including precisely positioned pads and alignment marks that guide the placement of stacked integrated circuits. This preliminary action ensures accurate positioning before soldering, preventing misalignment and improving connection reliability while maintaining manufacturing simplicity.
Solution Approach 2:
The patent uses a composite interconnect structure combining copper traces on the substrate with lead-free solder alloy balls. This composite material approach provides both mechanical strength to prevent lead pullouts and reliable electrical connection, while the solder ball geometry facilitates self-alignment during assembly, enhancing reliability without complicating manufacturing.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.