Flip Chip Pad Geometry for IC Package Substrates
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Solution Overview
Problem
Conventional IC package substrates with a matrix of pads are expensive to manufacture due to the need for an expensive solder on pad (SOP) process, especially when dealing with flip chip IC dies that have conductive elements throughout their active surface in a matrix configuration, as they require additional solder for reliable connections and multiple layers for routing without intersecting traces.
Innovation Solution
The development of an IC package substrate featuring a matrix of pillars that route connections without the need for an expensive SOP process, where each pillar is coupled to a respective pad on a metal layer and via, facilitating wetting with conductive elements using a solder reflow process without additional solder, and allowing for multiple layers of routing without intersecting traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional substrates include a matrix of pads with SOP process, then reliable connections are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive SOP pads with inexpensive solder balls that are applied directly to conductive elements. The solder balls serve as temporary connection media during reflow processing, eliminating the need for costly SOP process and specialized pad structures while achieving reliable connections through standard reflow techniques
Solution Approach 2:
The patent extracts and eliminates the SOP process from the manufacturing flow by using direct solder ball attachment to conductive elements. This removes the expensive intermediate pad structure and SOP processing step, retaining only the essential connection function through simplified direct soldering
2Device complexity
If pads are arranged in BoL configuration, then routing is simplified, but interior traces intersect with other traces when IC die has matrix configuration
Solution Approach 1:
The patent transitions from planar 2D trace routing to 3D vertical routing by introducing vias that pass through the substrate. This allows connections to route beneath conductive elements rather than crossing them on the same plane, eliminating trace intersections while maintaining routing simplicity
Solution Approach 2:
The patent implements nested routing where traces are arranged in layers with lower-layer traces positioned beneath upper-layer conductive elements. The via structures nest through the substrate to connect different layers, allowing dense matrix configurations without trace intersections
3Quantity of substance
If IC die has conductive elements throughout active surface in matrix configuration, then connection density increases, but conventional BoL pad configuration becomes unsuitable
Solution Approach 1:
The patent creates a universal substrate structure with an array of vias that can accommodate any conductive element pattern on the IC die, whether peripheral or full-matrix configuration. The via array provides multi-functional routing capability that adapts to different die layouts without requiring specialized pad configurations
Solution Approach 2:
The patent changes the fundamental parameter of connection architecture from BoL (bond-on-lead) to SOP (solder-on-pad) with direct solder ball attachment. This parameter change enables support for high-density matrix configurations by providing individual connection points throughout the substrate area rather than limited peripheral connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces manufacturing costs by eliminating the need for the SOP process while ensuring reliable connections and efficient routing of connections from IC dies with matrix configurations, enhancing the reliability and efficiency of IC package substrates.
Implementation Method 1
the IC die can be pressed against the IC package substrate and heated in a reflow oven such that the solder melts
Implementation Method 2
facilitating wetting with conductive elements using a solder reflow process
Data Source
AI summary
An integrated circuit (IC) package substrate is provided. In one embodiment, the IC package substrate includes a dielectric layer having first and second opposing surfaces and a matrix of pillars disposed in the dielectric layer and arranged to receive a matrix of conductive elements of an IC die. Each pillar of the matrix of pillars is exposed at the first surface of the dielectric layer. Each pillar of the matrix of pillars extends through the dielectric layer to contact a metal layer attached to the second surface of the dielectric layer.