Flip Chip Passive Device Formation Without Photolithography
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Solution Overview
Problem
The formation of passive circuit elements on semiconductor die introduces particles and contaminants through photolithographic processes, leading to defects and reduced manufacturing yield.
Innovation Solution
A method of forming semiconductor devices without photolithography, involving layer-by-layer deposition of conductive, resistive, and insulating layers to create passive devices like capacitors and resistors, ensuring that these layers are isolated from contaminants until after their formation, thereby reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processes are used to form passive circuit elements, then manufacturing precision and device complexity are improved, but particles and contaminants are introduced leading to reduced reliability
Solution Approach 1:
The manufacturing process is segmented into distinct phases: first forming the insulating and conductive layers without photolithography, then applying photolithography only to form the resistor pattern afterward. This segmentation isolates the contamination-sensitive layers from the contaminating photolithography process, resolving the contradiction between manufacturing precision and reliability.
Solution Approach 2:
The insulating layers and conductive layers are formed in advance before the photolithography process is applied. By performing these critical layer formations preliminarily, the patent ensures that contamination-sensitive structures are already in place and protected, allowing subsequent photolithography to only affect the resistor formation area.
2Manufacturing precision
If photolithographic processes are used to form passive circuit elements, then manufacturing precision is improved, but manufacturing yield deteriorates due to introduced contaminants
Solution Approach 1:
The process is divided into contamination-free phases (insulator and conductor layer formation) and contamination-prone phases (photolithography for resistor patterning). This segmentation allows the critical layers to be formed without contaminants, preserving manufacturing yield while still achieving precision where needed.
Solution Approach 2:
Critical layers are formed preliminarily before photolithography is applied. This preliminary action ensures that the most contamination-sensitive structures are already in place, so subsequent photolithography steps cannot introduce contaminants into them, thereby maintaining high manufacturing yield.
3Reliability
If layer-by-layer deposition without photolithography is used, then reliability is improved by avoiding contaminants, but manufacturing precision may deteriorate
Solution Approach 1:
The patent segments the process so that layer-by-layer deposition (without photolithography) is used for forming insulating and conductive layers where reliability is critical, while photolithography is reserved for resistor patterning where precision is needed but contamination impact is minimized.
Solution Approach 2:
Different manufacturing approaches are applied to different parts of the device: contamination-free layer-by-layer deposition is used for the capacitor structure where reliability is paramount, while photolithography is applied locally only for resistor patterning where geometric precision is needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and improves manufacturing yield by avoiding contamination during the formation of passive circuit elements, enabling the creation of high-density, reliable integrated circuits with improved circuit performance.
Implementation Method 1
The solder bumps are formed by a reflow process applied to solder material deposited on contact pads
Data Source
AI summary
A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.