Multi-Die Flip Chip Package Using Pillar Bumps
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Solution Overview
Problem
Conventional 3D-packaging methods using metal bonding wires for electrical connections in multi-die packages face limitations such as increased area requirements, high resistance, parasitic effects, and high costs due to wire span and contact pad restrictions, which hinder miniaturization and are unsuitable for high-power systems.
Innovation Solution
A multi-die package configuration utilizing flip chip dies stacked vertically with pillar bumps for electrical coupling, eliminating the need for bonding wires by directly connecting the dies through a lead frame structure, allowing for more compact and efficient electrical communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal bonding wires are used for electrical connections in multi-die packages, then electrical communication between stacked dies can be established, but the package area increases due to wire span and contact pad requirements
Solution Approach 1:
The patent extracts and eliminates the metal bonding wires from the packaging system, replacing them with a wireless flip-chip interconnect architecture. This removal of the wire bonding component directly resolves the area occupation problem while maintaining electrical connectivity through alternative means (substrate traces and contact pads).
Solution Approach 2:
The patent replaces the mechanical wire bonding system with an electrical field-based connection system. Instead of using physical metal wires that require space for routing and bonding, the invention uses electrical signals transmitted through substrate traces, eliminating the need for mechanical wire spans and associated contact pads.
2Reliability
If metal bonding wires are used for electrical connections, then electrical communication can be established, but resistance and parasitic effects increase which is unsuitable for high power systems
Solution Approach 1:
The patent replaces the mechanical wire bonding system with an integrated electrical connection system using substrate traces. This substitution eliminates the long, thin metal wires that inherently possess resistance and parasitic inductance, replacing them with optimized trace routes on the substrate that have lower impedance and reduced parasitic effects, making the system suitable for high-power applications.
Solution Approach 2:
The patent transitions from three-dimensional wire routing (requiring vertical wire spans between dies) to a two-dimensional trace-based connection system on the substrate plane. This dimensional change allows for optimized signal paths with fewer discontinuities and lower parasitic effects, while maintaining electrical communication between stacked dies.
3Reliability
If wire bonding technology is used, then electrical connections can be made, but manufacturing cost and process time increase due to gold wires and layer-by-layer fabrication
Solution Approach 1:
The patent extracts and eliminates the expensive gold wire bonding process from the manufacturing workflow. By removing this complex, multi-step wire bonding operation, the invention significantly reduces both material costs (eliminating gold wire usage) and manufacturing time (removing layer-by-layer wire placement and bonding steps), while maintaining reliable electrical connections through the wireless flip-chip architecture.
Solution Approach 2:
The patent changes the manufacturing parameters from precision wire bonding (requiring controlled wire tension, bonding temperature, and ultrasonic parameters) to standard PCB trace fabrication and flip-chip mounting processes. This parameter change simplifies the manufacturing process, reduces cycle time, and eliminates the need for expensive gold materials while maintaining connection reliability.
Data Source
AI summary
The present technology discloses a multi-die package. The package comprises a lead frame structure and three dies including a first flip chip die, a second flip chip die and a third flip chip die stacked vertically. The first flip chip die is mounted on the bottom surface of the lead frame structure through the flip chip bumps; the second flip chip is mounted on the top surface of the first flip chip die through flip chip bumps; and the third flip chip die is mounted on the top surface of the lead frame structure through flip chip bumps.