Flip Chip Post Connect Assembly for Reduced Solder Bump Pitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in packaging semiconductor devices is to accommodate smaller silicon dies with tighter pitch requirements for post connect and solder bump spacing, while minimizing costs and maintaining efficient manufacturing processes.
Innovation Solution
The solution involves forming bond pads on a semiconductor die, depositing a passivation layer with openings over the bond pads, and using a plating process to create post connects with solder bumps. The solder bumps are formed by depositing solder on the distal ends of the post connects, which contact the sidewalls of the openings in the passivation layer and extend over the planar surface, allowing for reduced pitch distances and solder volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch distance between post connects is reduced to accommodate smaller dies, then the die area is reduced and manufacturing efficiency is improved, but the manufacturing precision and reliability of solder joints deteriorate due to processing limitations
Solution Approach 1:
The patent segments the formation process into two distinct stages: first forming the post connects through plating, then separately forming the solder bumps through deposition and reflow. This segmentation allows each feature to be optimized independently, enabling reduced pitch distances while maintaining manufacturing precision for both post connects and solder bumps.
Solution Approach 2:
The patent performs preliminary action by forming the post connects first, then using them as templates for subsequent solder bump formation. The post connects are prepared in advance with proper spacing, and the solder bumps are later deposited onto them, allowing the pitch to be determined by the more precise plating process rather than being constrained by solder bump processing limitations.
2Productivity
If the pitch distance between post connects is reduced, then more connections can be accommodated on smaller dies, but the process complexity increases due to additional plating and deposition steps
Solution Approach 1:
The patent merges multiple functions into the plating process: the same plating step that forms the post connects also creates the foundation for solder bump formation. The seed layer deposition and solder paste application are then performed, followed by a single reflow process that simultaneously completes both the electrical connection and mechanical attachment functions.
Solution Approach 2:
The post connects serve multiple functions: they provide the structural foundation for solder bump attachment, act as electrical conductors, and serve as spacing templates for the solder bumps. The plating process itself is multi-functional, creating both the post connect structure and the base for subsequent solder deposition.
3Reliability
If larger die area is used to meet spacing requirements, then the pitch distance between post connects can be maintained, but the manufacturing cost increases due to reduced wafer yield
Solution Approach 1:
The patent changes the controlling parameter for pitch distance from solder bump processing limitations to plating process capabilities. By using plating to form post connects first, then depositing solder bumps onto them, the pitch can be reduced to values that would be impossible with traditional simultaneous formation methods, thereby increasing wafer yield while maintaining solder joint reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of smaller silicon dies with reduced pitch distances between solder bumps and post connects, thereby decreasing costs and improving manufacturing efficiency while maintaining reliable electrical and mechanical connections.
Implementation Method 1
performing a plating process to form post connects on the bond pads and in the openings
Implementation Method 2
the solder bumps are subjected to a thermal reflow process so that the solder melts and flows to form solder joints
Data Source
AI summary
A described example includes: a semiconductor die having bond pads on a device side surface; a passivation layer overlying the device side surface of the semiconductor die with openings in the passivation layer, the passivation layer having a planar surface facing away from the device side surface of the semiconductor die; post connects formed on the bond pads and in the openings in the passivation layer, the post connects having a proximate end on the bond pads and extending from the bond pads to a distal end that lies beneath the planar surface of the passivation layer; solder at the distal ends of the post connects and contacting sidewalls of the openings in the passivation layer; and solder joints formed between the solder at the distal ends of the post connects and a package substrate, the device side surface of the semiconductor die facing the package substrate.