Flip Chip Post Connect Assembly for Fine-Pitch Solder Joints
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Solution Overview
Problem
The challenge of reducing the pitch distance between conductive post connects and solder bumps in flip chip packages is exacerbated by the limitations of photolithography, leading to increased die size and costs due to the need for larger silicon dies to accommodate spacing requirements, which reduces the number of dies per wafer and increases production costs.
Innovation Solution
The formation of post connects with a proximate end on bond pads and a distal end beneath a passivation layer, followed by solder deposition and plating to form solder bumps, utilizing laser ablation for precise pitch control and reduced solder volume, allowing for smaller die sizes and reduced pitch distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to form post connects and solder bumps, then manufacturing process is simple, but pitch distance cannot be reduced below minimum requirements
Solution Approach 1:
The patent replaces photolithography (optical system) with direct laser writing (laser system) to form post connects and solder bumps. This substitution enables precise control of pitch distance without being constrained by photolithography minimum feature sizes, directly resolving the contradiction between achieving smaller pitch and maintaining manufacturing simplicity.
Solution Approach 2:
The patent changes the manufacturing parameters by using laser-based direct writing instead of photolithographic patterning. This parameter change allows continuous control of pitch distance through laser positioning, enabling pitch distances smaller than what photolithography can achieve while maintaining a relatively simple manufacturing process.
2Manufacturing precision
If die area is increased to meet spacing requirements, then pitch distance between post connects is sufficient, but number of dies per wafer decreases and cost increases
Solution Approach 1:
By replacing photolithography with direct laser writing, the patent enables formation of post connects and solder bumps at smaller pitch distances. This allows bond pads to be placed closer together on the die, increasing the number of dies that can be fabricated per wafer while maintaining adequate spacing for reliable connections.
Solution Approach 2:
The patent introduces vertical integration by forming post connects that extend through the die thickness and solder bumps that connect to substrate pads. This three-dimensional approach allows closer spacing of bond pads on the die surface while maintaining connection integrity, effectively increasing die density per wafer.
3Manufacturing precision
If solder bump volume is reduced, then material cost and pitch distance are reduced, but reliability of solder joints may be compromised
Solution Approach 1:
The patent uses direct laser writing to form solder bumps with precise control over volume and geometry. This enables optimization of solder bump size to the minimum required for reliable joints, reducing excess material while ensuring adequate mechanical and electrical connection. The laser process provides precise control of solder distribution and joint formation.
Solution Approach 2:
The patent applies local optimization by forming solder bumps with precisely controlled volume and shape at each connection point. Rather than using uniform oversized bumps, the laser process enables tailored solder volumes matched to local connection requirements, reducing overall solder material while maintaining joint reliability where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables smaller semiconductor dies with reduced pitch distances and solder volume, decreasing production costs and increasing package design flexibility by allowing multiple bond pads to be coupled to a single solder bump, thereby improving manufacturing efficiency.
Implementation Method 1
utilizing laser ablation for precise pitch control
Implementation Method 2
the solder melts and flows to form solder joints
Implementation Method 3
the solder melts and flows to form solder joints. The solder joints mechanically attach and electrically couple the semiconductor die to the package substrate
Data Source
AI summary
A described example includes: a semiconductor die having bond pads on a device side surface; a passivation layer overlying the device side surface of the semiconductor die with openings in the passivation layer, the passivation layer having a planar surface facing away from the device side surface of the semiconductor die; post connects formed on the bond pads and in the openings in the passivation layer, the post connects having a proximate end on the bond pads and extending from the bond pads to a distal end that lies beneath the planar surface of the passivation layer; solder at the distal ends of the post connects and contacting sidewalls of the openings in the passivation layer; and solder joints formed between the solder at the distal ends of the post connects and a package substrate, the device side surface of the semiconductor die facing the package substrate.