Flip-Chip Solder Joint Recess Layout for Thermal Stress Relief

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flip-chip packaged electronic devices experience solder joint failures due to mechanical stress caused by thermal expansion and contraction of materials with different coefficients of thermal expansion, leading to reliability issues during stress testing.

Innovation Solution

Incorporating stress relief structures, such as recesses or protrusions, on the package substrate to reduce mechanical stress on solder joints by spacing them away from the material interface between the mold compound and the substrate, thereby protecting the joints from thermal mechanical stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flip-chip packaged devices are stress tested with repeated temperature cycling, then component level reliability can be evaluated, but solder joint failures occur due to thermal mechanical stress from differential thermal expansion

Engineering Contradiction:
Improvecomponent level reliabilityVSAvoidthermal mechanical stress on solder joints
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary stress relief structure (recess or protrusion) between the mold compound and the solder joint. This intermediary element absorbs and redistributes the thermal mechanical stress generated by differential thermal expansion between materials, protecting the solder joint from direct stress while allowing reliability testing to proceed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The stress relief structure is pre-formed in the package substrate before the soldering process. This beforehand cushioning structure is positioned to intercept and mitigate thermal mechanical stress before it reaches the solder joint during subsequent temperature cycling, preventing solder joint failure before it occurs

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If stress relief structures are incorporated into the package substrate, then solder joint reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesolder joint reliabilityVSAvoidpackage substrate structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress relief structure is implemented as a localized feature (recess or protrusion) at specific positions in the package substrate where stress concentration occurs, rather than modifying the entire substrate. This localized approach provides targeted stress relief while minimizing overall device complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The stress relief structure modifies local geometric parameters of the package substrate (creating recesses or protrusions with specific dimensions and positions). These parameter changes create stress-relieving zones that protect solder joints without fundamentally altering the overall device architecture or requiring complex additional components

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of stress relief structures significantly reduces solder joint failures during accelerated stress testing, enhancing the reliability of flip-chip packaged electronic devices by mitigating thermal mechanical stress.

Implementation Method 1

the solder bumps at the distal end of the post connects are heated and allowed to reflow to form solder joints that provide a mechanical connection and electrically couple the semiconductor device die to the package substrate

Methodology Applied
Scientific EffectSolder reflow: Soldering

Implementation Method 2

Due to the use of materials in the packages with different coefficients of thermal expansion (CTE), including semiconductor substrates, package substrates, solder and mold compound, the materials expand and contract at different rates

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11930590B2Stress relief for flip-chip packaged devices
Publication Date: 2024.03.12 TEXAS INSTRUMENTS INC
  • US11930590B2 patent drawing
  • US11930590B2 patent drawing
  • US11930590B2 patent drawing

AI summary

In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.