Automated Flip Chip Routing via Bump Projections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for determining flip chip connections are labor-intensive and time-consuming, often requiring manual intervention and cannot automatically correct errors like crossing connections or congestion, especially when working within a single redistribution layer.
Innovation Solution
An automated method that generates projections of bumps and I/O pads to determine connections between them, allowing for hierarchical adjustments to prevent crossings and congestion, and implements these connections within a single redistribution layer using integrated tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual methods are used to assign nets, place pads and draw wires, then design flexibility is maintained, but labor time and complexity increase significantly
Solution Approach 1:
The system performs automatic net assignment, pad placement, and wire routing without requiring manual intervention. The computer automatically determines optimal connections between bumps and I/O pads, eliminating the need for designers to manually assign nets and place pads, thereby reducing design time while maintaining quality through algorithmic optimization
Solution Approach 2:
The patent replaces manual mechanical design processes with an automated computer-based system. The mechanical action of manually drawing wires and placing pads is substituted with automated algorithms that compute optimal routing paths and pad assignments, dramatically reducing design time and labor requirements
2Adaptability or versatility
If more than one redistribution layer is used to complete routing, then routing flexibility increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs sophisticated two-dimensional routing algorithms that can navigate complex routing scenarios within a single layer by utilizing available space efficiently. The system performs automatic net assignment, pad placement, and wire routing within one redistribution layer, eliminating the need for multiple layers while maintaining routing flexibility through advanced computational methods
Solution Approach 2:
The system changes the approach from using multiple layers (vertical dimension) to optimizing routing within a single layer (horizontal dimension). By altering the routing parameters and using advanced algorithms to maximize space utilization in one layer, the patent achieves the same routing flexibility without increasing manufacturing complexity
3Productivity
If automated tools are used for bump assignment and pad placement, then productivity increases, but ability to handle complex constraints decreases
Solution Approach 1:
The system incorporates feedback mechanisms where the automated tool evaluates routing results and iteratively adjusts net assignments and pad placements to satisfy complex constraints. The computer-based system can detect constraint violations and automatically refine the design, combining the speed of automation with the ability to handle complex design requirements through iterative optimization
Solution Approach 2:
The patent implements dynamic constraint handling where the automated system can adapt to different design scenarios and constraints. The algorithm dynamically adjusts its optimization criteria based on the specific design requirements, allowing it to handle complex constraints while maintaining high productivity through automated processing
Data Source
AI summary
An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad. The outer portion of the flip chip is traversed, and the second projection is generated based on the order in which I/O pad representations are encountered. Connections between bump and I/O representations are made and connecting between bumps and I/O pads determined based on the connections between bump and I/O pad representations of respective first and second projections. The determined connections can be adjusted according to a hierarchy of bump representations to reduce or eliminate congestion, e.g., by changing a sequence of or deleting bump representations.