Flip Chip System in Package Testing and Bonding

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Solution Overview

Problem

Conventional System In Package (SIP) fabrication methods require individual testing of semiconductor chips, leading to reduced production yields due to faulty chips, and stacking packages instead increases device thickness, contradicting the goal of smaller, lighter electronic devices.

Innovation Solution

A method for fabricating a system in package that involves testing and sorting semiconductor chip stacks before flip chip bonding, ensuring only reliable chips are used, thereby preventing faulty chip impacts and maintaining package thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If individual testing of semiconductor chips is performed in conventional SIP fabrication, then faulty chips can be identified, but production yields are reduced due to the strict requirement that all chips must be good

Engineering Contradiction:

Improvechip reliabilityVSAvoidproduction yield

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The invention segments the testing process by testing only one chip in the stack rather than all chips, and segments the package structure into a stack of multiple chips on a single PCB. This allows the system to tolerate some faulty chips while maintaining overall functionality, thereby improving production yield without completely sacrificing reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the reliability parameter from requiring 100% good chips to accepting a certain proportion of good chips (e.g., one good chip out of multiple stacked chips). This parameter change allows production to continue even when not all chips pass testing, thus improving productivity while maintaining acceptable reliability levels.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If packages are stacked instead of individual chips to ensure reliability, then faulty chip impacts are prevented, but device thickness increases significantly

Engineering Contradiction:

Improvesystem reliabilityVSAvoidpackage thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The invention transitions from stacking packages in the vertical dimension to stacking chips within a single package footprint. By placing multiple chips on the same PCB in a stacked configuration rather than creating separate packages, the solution maintains reliability through redundancy while avoiding the thickness increase that would result from stacking entire packages.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention nests multiple semiconductor chips within a single package structure, with chips stacked vertically on the PCB and enclosed by a single encapsulant. This nested configuration provides redundancy for reliability while maintaining a compact form factor that does not significantly increase overall package thickness compared to conventional single-chip packages.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Productivity

If multiple chips are stacked on a single PCB, then production efficiency is improved, but testing complexity increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidtesting complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The invention extracts the testing requirement from applying to all chips in the stack and applies it to only one representative chip. This extraction of the testing obligation reduces testing complexity and time while still providing quality assurance for the entire stack, thereby supporting improved production efficiency without excessive testing burden.

Inventive Principle:

Principle #2Taking out (Extraction)

4Stability of the object's composition

If conventional individual package fabrication is used, then each package is self-contained, but production rates are reduced due to individual testing requirements

Engineering Contradiction:

Improvepackage independenceVSAvoidproduction rate

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The invention merges multiple chip packages into a single integrated package structure where multiple chips share common packaging elements such as the PCB substrate and encapsulant. This merging allows for more efficient production processes and reduced testing requirements compared to fabricating and testing multiple separate packages, thereby improving production rate while maintaining functional independence of each chip through individual bonding and electrical isolation.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7776650B2Method for fabricating a flip chip system in package

Publication Date: 2010.08.17 SAMSUNG ELECTRONICS CO LTD

AI summary

Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.