Flip-Chip SOA-PIN Integration With Planar Contacts for High Frequency
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Solution Overview
Problem
Existing optoelectronic devices face challenges in achieving high frequency performance due to mechanical weakness, thermal resistivity, and difficulty in patterning small diodes, particularly in SOA-PIN integrated devices with non-planar structures and mismatched metal contacts.
Innovation Solution
A one-step process for integrating a SOA and PIN on a semi-insulating wafer with planarized metal contacts, using a Semi-Insulating Buried Heterostructure (SIBH) design, where the p and n contacts are at the same level, and employing regrown semi-insulating stacks to facilitate easy soldering and heat evacuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a non-planar SIBH structure is used with different crystallographic plane growths, then the optoelectronic device can be manufactured using a one-step process, but the device exhibits mechanical weakness and poor heat evacuation
Solution Approach 1:
The patent changes the geometric parameters of the structure by introducing trenches that extend through the active layers to the substrate. This modification transforms the non-planar surface into a planar structure with controlled depth and width parameters, thereby improving mechanical strength and heat evacuation while preserving the one-step manufacturing advantage
Solution Approach 2:
The patent segments the structure by introducing trenches that divide the active layers into isolated regions. This segmentation allows the trenches to serve multiple functions: providing mechanical support, creating pathways for heat evacuation, and enabling planarization of the surface for subsequent metal contact deposition
2Strength
If resin encapsulation is used to avoid mechanical weakness, then the device structure is protected, but thermal resistivity increases and heat evacuation is penalized
Solution Approach 1:
The patent extracts the heat evacuation function from the resin encapsulation by introducing dedicated trench structures that provide thermal pathways. These trenches are filled with materials having high thermal conductivity, thereby separating the mechanical protection function (performed by the overall device structure) from the heat evacuation function (performed by the trench structures), eliminating the need for resin encapsulation
3Ease of manufacture
If metal contacts are placed at different levels to accommodate non-planar structure, then the device can be manufactured, but additional pillars are required for via contacts
Solution Approach 1:
The patent creates equipotential surfaces by forming trenches that extend to the substrate level, thereby establishing a planar reference plane across the entire device surface. This allows all metal contacts to be deposited at the same level without requiring additional pillars or via structures, simplifying the overall device architecture while maintaining manufacturability
4Speed
If the PIN diode size is reduced to reach higher frequencies, then the frequency response is improved, but patterning difficulty increases
Solution Approach 1:
The patent transitions from two-dimensional lateral scaling to three-dimensional vertical structuring by introducing trenches that extend through the active layers. This dimensional change allows the PIN diode active area to be reduced for high-frequency operation while the trench depth and width provide additional degrees of freedom for controlling electrical and thermal properties, thereby maintaining manufacturability
Data Source
Figure 1~3a
Figure 3b1~3b5
Figure 3c~5b
AI summary
An integrated optoelectronic device D wherein a SOA and PIN are integrated on the same semi-insulating wafer in order to reach high frequency, and wherein the manufacture of such a device is based on a one-step process of making a semi-insulating buried heterostructure (SIBH) where the p and n contacts are at the same level on the same wafer face and can be easily soldered to the package of the flip-chip package.