Intermetallic Compound Layer Control in Flip Chip Solder Joints
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Solution Overview
Problem
The increasing demand for smaller, more functional, and cost-effective integrated circuits with higher I/O density poses challenges such as thermal expansion mismatches between integrated circuits and substrates, leading to reliability issues and weak solder joints in flip chip packaging, particularly due to the brittleness of intermetallic compound layers.
Innovation Solution
The electronic system involves forming a substrate with conductive structures and conductive protrusions, where a conductive core with a transition cover is used to enhance solder joint strength by limiting crack propagation and distributing intermetallics, thereby improving attachment reliability and reducing the brittleness of the solder joint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flip chip packaging with coined SOP is used to achieve fine bump pitch and small bump pad diameter, then I/O density is improved, but the brittleness of intermetallic compound layers increases causing weak solder joints
Solution Approach 1:
The patent applies local quality by creating a non-uniform intermetallic compound layer with varying thickness across the solder joint area. The IMC layer is thinner at the center and thicker at the periphery, providing localized strength where needed while maintaining overall joint integrity. This gradient structure addresses the brittleness issue by distributing stress more effectively throughout the joint.
Solution Approach 2:
The patent employs composite materials by combining multiple metal layers (copper, nickel, palladium, and solder alloy) to create a multi-layered intermetallic compound structure. This composite approach allows each layer to contribute specific properties: copper provides conductivity, nickel offers structural stability, and the solder alloy creates strong bonding, collectively improving solder joint strength while maintaining high I/O density.
2Strength
If elevated temperatures are applied during reflow to form solder connections, then electrical and mechanical connections are improved, but thermal expansion mismatch between integrated circuit and substrate increases causing reliability problems
Solution Approach 1:
The patent applies parameter changes by carefully controlling the reflow temperature profile and composition of the solder alloy to optimize the formation of intermetallic compounds. By adjusting temperature parameters and material composition, the patent achieves strong solder connections while minimizing excessive IMC growth that would cause brittleness and reliability issues during thermal cycling.
3Strength
If intermetallic compound layers are formed to ensure good solder joint, then bonding is improved, but the thickness of IMC layers increases causing weakness and brittleness
Solution Approach 1:
The patent applies local quality by creating a non-uniform intermetallic compound layer with varying thickness across the solder joint area. The IMC layer is thinner at the center and thicker at the periphery, providing localized strength where needed while maintaining overall joint integrity. This gradient structure addresses the brittleness issue by distributing stress more effectively throughout the joint.
Solution Approach 2:
The patent applies partial action by forming intermetallic compound layers with controlled, limited thickness rather than allowing excessive IMC growth. The reflow process is optimized to create just enough IMC layer to ensure good bonding while preventing the layer from becoming too thick and brittle. This controlled partial formation maintains the balance between bonding strength and joint reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and strength of solder joints by using a conductive core with a transition cover, which spreads intermetallics and reduces the brittleness of the intermetallic compound layer, addressing the issues of thermal expansion mismatches and improving manufacturing yield and cost-effectiveness.
Implementation Method 1
Typical flip chip bonding techniques utilizes coined SOP (Solder On Pad) due to wetting capability and uniformity of height. However, in the case of conventional SOP, the failure caused by a crack in the SOP due to stress from the coefficient of thermal expansion (CTE) mismatch between underfill and substrates at intermetallic compound (IMC) layer.
Implementation Method 2
Typical flip chip bonding techniques utilizes coined SOP (Solder On Pad) due to wetting capability and uniformity of height.
Implementation Method 3
These elevated temperatures may cause the integrated circuits and the carrier to expand at different rates creating problems at the contact points.
Implementation Method 4
the failure caused by a crack in the SOP due to stress from the coefficient of thermal expansion (CTE) mismatch between underfill and substrates
Data Source
AI summary
An electronic system is provided including forming a substrate having a contact, forming a conductive structure over the contact, mounting an electrical device having an external interconnect over the conductive structure, and forming a conductive protrusion from the conductive structure in the external interconnect.