Flip Chip Solder Mask for Wetting Control
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Solution Overview
Problem
Conventional flip chip packaging techniques struggle with precise control over solder bump height and spacing, leading to issues like excessive solder wetting, reduced collapse height, poor IC planarity, solder overflow, and insufficient lead registration, which hinder the development of smaller, more functional integrated circuits at lower costs.
Innovation Solution
An integrated circuit package system with interconnect support, featuring a chip support structure that includes a paddle and tie bar configuration, where the integrated circuit is mounted on a chip support during reflow to prevent collapse and ensure proper spacing, and an epoxy molding compound encapsulates the components to maintain stability and prevent solder contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reflow solder techniques are used to solder flip chip to conductor pattern, then electrical connection is achieved, but solder bump height control is poor leading to excessive solder wetting and overflow
Solution Approach 1:
The patent applies preliminary action by depositing a solder mask layer over the conductor pattern before the reflow soldering process. This solder mask layer is formed in advance to define precise solder deposit areas and control solder flow during reflow, preventing excessive wetting and overflow while maintaining proper solder bump height
Solution Approach 2:
The solder mask layer serves as an intermediary between the solder material and the conductor pattern. It controls where solder can flow and how much solder can wet the conductor, acting as a mediator that prevents harmful solder overflow while allowing proper electrical connection in controlled areas
2Manufacturing precision
If solder is deposited at each terminal location, then electrical connection is formed, but spacing between chip and substrate cannot be closely controlled
Solution Approach 1:
The solder mask layer acts as an intermediary that controls both solder deposition and chip-to-substrate spacing. By designing the solder mask with specific thickness and pattern, it simultaneously controls where solder is deposited and maintains proper spacing between the chip and substrate, simplifying the overall control process
Solution Approach 2:
The solder mask layer performs multiple functions: it defines conductor patterns, controls solder deposit areas, regulates solder bump height, and maintains chip-to-substrate spacing. This multi-functional approach reduces device complexity by consolidating multiple control functions into a single layer
3Area of stationary object
If fine conductor patterns are used to accommodate crowded terminals, then area is reduced, but soldering precision requirements increase significantly
Solution Approach 1:
The solder mask layer serves as a mediator that enables fine conductor patterns to be used effectively. It provides a controlled environment for solder deposition on fine conductors, preventing solder overflow onto adjacent conductors and reducing the precision burden on the soldering process itself
4Manufacturing precision
If solder bump height is increased to provide proper positioning, then chip positioning is improved, but solder wetting becomes excessive
Solution Approach 1:
The solder mask layer acts as an intermediary that decouples solder bump height from solder wetting control. It allows tall solder bumps to be formed for proper chip positioning while preventing excessive lateral spread and wetting of the conductor pattern through its confining structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances chip planarity, reduces solder contamination, and supports the trend of reducing costs while increasing performance by providing better control over solder wetting and collapse height, thus improving the packaging process for flip-chip QLP packages.
Implementation Method 1
an epoxy molding compound encapsulates the components to maintain stability and prevent solder contamination
Implementation Method 2
Heating the solder above its melting temperature serves to form the characteristic solder bumps
Implementation Method 3
reheating, or reflowing, the solder so as to metallurgically and electrically bond the chip to the conductor pattern
Implementation Method 4
forming solder bumps on the surface of the flip chip
Data Source
AI summary
An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.