Flip Chip Space Transformer for Multi-Chip Module Testing

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Solution Overview

Problem

Conventional space transformer solutions for testing integrated circuits face challenges in multi-chip modules, where longer electrical routing lengths exceed circuit drive capabilities and increased I/Os complicate traditional test approaches, limiting test capabilities and efficiency.

Innovation Solution

Implementing a flip chip package as the space transformer during testing, which includes all necessary routing, reducing total routing length and enabling direct communication between DUT and peripheral chips through test probes, thereby simplifying the test system and improving electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional space transformer routing is used to connect DUT to tester, then electrical contact is established, but routing length becomes significantly longer than drive capabilities of circuits

Engineering Contradiction:

Improveelectrical contactVSAvoidrouting length

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent transitions from planar routing on a flat space transformer substrate to three-dimensional vertical routing through multi-chip module stacking. Test probes connect directly to dice through vertical pathways, eliminating long horizontal routing traces and reducing overall signal path length while maintaining electrical contact reliability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds the space transformer functionality within the multi-chip module structure itself. The routing layers are nested between functional chips, and test probes are integrated into the module assembly, allowing test signals to access dice through compact internal pathways rather than external routing

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If all additional I/Os are tested in multi-chip packaging, then complete test coverage is achieved, but routing on space transformer becomes more complicated and requires additional test resources

Engineering Contradiction:

Improvetest coverageVSAvoidrouting complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the testing function from the conventional space transformer architecture and implements it directly through integrated test probes that access dice within the multi-chip module. This eliminates the need for complex external routing networks and additional test resources while maintaining complete I/O test coverage

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The multi-chip module structure serves multiple functions simultaneously: it provides both the functional integration of multiple chips and the test access mechanism through integrated probes. The same vertical routing pathways serve both signal interconnection and test signal delivery, reducing overall system complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10101381B2Space transformation methods

Publication Date: 2018.10.16 INTEL CORP

AI summary

A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.