Flip Chip Contact Layout With Split I/O and Power Routing
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Solution Overview
Problem
Existing chip packaging technologies face challenges in accommodating increasing numbers of I/O and power contacts due to fixed locations of contacts, which constrain modularization and routing flexibility, especially with high-speed signals and power delivery planes overlapping, limiting the feasibility of memory module placement and system design flexibility.
Innovation Solution
A chip package design with I/O contacts on one surface layer and power contacts on an opposite layer, allowing for separation and flexible routing, and connections to a PCB at locations other than the chip receiving area, enabling increased contact numbers and modularization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O contacts and power contacts are arranged on the same surface layer, then the contact density increases, but the routing flexibility and placement options are constrained
Solution Approach 1:
The patent divides the contacts into two separate groups located on opposite surface layers: I/O contacts on the first surface layer and power contacts on the second surface layer. This segmentation allows each contact type to be independently routed and placed, resolving the contradiction by enabling high contact density while maintaining routing flexibility for each contact type separately.
Solution Approach 2:
The patent utilizes the vertical dimension by distributing contacts across multiple layers (first surface layer and second surface layer). This dimensional approach allows I/O and power contacts to coexist with high density while providing separate routing paths through different layers, thus maintaining adaptability.
2Ease of manufacture
If contact locations are fixed near the chip receiving area, then the connection is simplified, but the system layout becomes cluttered and modularization is constrained
Solution Approach 1:
The patent extracts the contact points from the traditional fixed location near the chip receiving area and relocates them to opposite surface layers. This extraction allows the contacts to be positioned optimally for their respective routing paths, simplifying the overall system layout and enabling modularization while maintaining manufacturing ease.
Solution Approach 2:
By moving contacts to different vertical layers, the patent creates spatial separation that simplifies routing without increasing layout complexity. The vertical dimension provides additional routing space, allowing clean separation of I/O and power paths.
3Quantity of substance
If additional layers are added to accommodate more contacts, then the contact capacity increases, but the package becomes less compact and cleaner
Solution Approach 1:
The patent utilizes the vertical dimension by placing contacts on opposite surface layers of the existing substrate, rather than adding more horizontal layers. This approach increases contact capacity while maintaining package compactness, as the solution leverages the existing vertical space of the substrate structure.
Data Source
AI summary
In one or more embodiments, a chip may be formed with a first set of contacts on a first surface layer and a second set of contacts on a second surface layer opposite the first surface layer. The first set of contacts may be communication (IO) contacts and the second set of contacts may be power contacts, including ball grid array (BGA) balls and capacitors. A PCB may be configured with a chip receiving area capable of receiving the second set of contacts for various chips.