Flip Light Emitting Chip Extended Stacking Layer
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Solution Overview
Problem
The manufacturing process of dual-ISO structural flip chips is complex and costly, involving multiple photoetching processes that can affect the stability and reliability of the final product.
Innovation Solution
A simplified manufacturing method for flip light-emitting chips that includes forming an extended stacking layer on a substrate, a reflective layer on the P-type semiconductor layer, a barrier layer covering the reflective layer, a bonding layer between the barrier and insulating layers to enhance binding force, and a first insulating layer with channels to expose semiconductor and barrier layer surfaces for electrode connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple photoetching processes are used to manufacture dual-ISO structural flip chips, then the manufacturing precision and reliability are improved, but the device complexity and production cost increase
Solution Approach 1:
The patent combines multiple photoetching processes into a single integrated manufacturing step. The insulating layer is formed with multiple functional regions (first insulating region, second insulating region, third insulating region) in one process, eliminating the need for separate photoetching steps for each region. This merging approach maintains the complex multi-region structure while simplifying the manufacturing process and reducing production costs.
2Manufacturing precision
If multiple photoetching processes are used to manufacture dual-ISO structural flip chips, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent performs preliminary structuring of the insulating layer before final electrode formation. The insulating layer is pre-formed with designated regions (first, second, and third insulating regions) that define future electrode positions and configurations. This preliminary action allows subsequent electrode formation to proceed more efficiently without requiring multiple iterative photoetching steps, thereby improving productivity while maintaining manufacturing precision.
3Strength
If a bonding layer is added between barrier layer and insulating layer, then the strength is improved, but the device complexity increases
Solution Approach 1:
The patent introduces a bonding layer as an intermediary between the barrier layer and the insulating layer. This bonding layer serves as a mediator that enhances the binding force and adhesion between these two layers. The bonding layer is integrated into the existing manufacturing process flow and works synergistically with the multi-region insulating structure, improving overall device strength without significantly increasing process complexity.
Data Source
AI summary
A flip light emitting chip and a manufacturing method thereof are provided. The flip light emitting chip includes a substrate and an extended stacking layer formed on the substrate. The extended stacking layer includes a first semiconductor layer formed on the substrate, an active region formed on the first semiconductor layer, and a second semiconductor layer formed on the active region. The flip light emitting chip further includes a reflective layer formed on the second semiconductor layer, a barrier layer formed on the second semiconductor layer and covering the reflective layer, a bonding layer formed on the barrier layer and an insulating layer formed on the bonding layer such that the bonding layer is retained between the barrier layer and the insulating layer for enhancing a binding force between the barrier layer and the insulating layer.