Flip-Chip Package Stress Relief Structure for Solder Joint Reliability
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Solution Overview
Problem
Flip-chip packaged electronic devices experience solder joint failures due to mechanical stress from thermal expansion and contraction of materials with different coefficients of thermal expansion, leading to scrapping during stress testing.
Innovation Solution
Incorporating stress relief structures, such as recesses or protrusions, on the package substrate to surround or partially surround the solder joints, reducing mechanical stress by spacing them away from the material interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip-chip packaged devices are stress tested with repeated temperature cycling, then component level reliability is evaluated, but solder joint failures occur due to mechanical stress from thermal expansion differences
Solution Approach 1:
The patent introduces stress relief structures that segment the continuous mold compound material into distinct regions: a first region surrounding the solder joint and a second region extending toward the die. This segmentation allows differential movement and stress distribution, reducing mechanical stress concentration at the solder joint during thermal cycling.
Solution Approach 2:
The stress relief structure acts as an intermediary element between the mold compound and the solder joint. It mediates the thermal expansion forces by providing a compliant interface that absorbs and distributes mechanical stress, protecting the solder joint from direct stress during temperature cycling.
2Stability of the object's composition
If mold compound covers the die and post connects, then package integrity is formed, but mechanical stress is applied to solder joints during thermal cycling
Solution Approach 1:
The patent applies local quality by creating a stress relief structure with specific geometric features (such as recesses or protrusions) at the localized region around the solder joint. This local structural modification provides stress relief precisely where needed without compromising the overall package integrity and mold compound coverage.
Solution Approach 2:
The stress relief structure is incorporated into the mold compound design before final packaging. This pre-configured structure provides cushioning and stress absorption capacity in advance, preparing the package to withstand thermal expansion forces during subsequent temperature cycling without damaging the solder joints.
3Adaptability or versatility
If materials with different coefficients of thermal expansion are used in the package, then functional requirements are met, but solder joint failures occur during stress testing
Solution Approach 1:
The patent addresses the thermal expansion mismatch by introducing a stress relief structure that modifies the mechanical parameters of the mold compound-solder joint interface. The structure changes the stress distribution parameters and compliance characteristics, allowing the package to accommodate different material thermal expansion rates without solder joint failure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces solder joint failures during thermal cycling, enhancing the reliability and longevity of flip-chip packaged devices by mitigating thermal mechanical stress.
Implementation Method 1
the solder bumps at the distal end of the post connects are heated and allowed to reflow to form solder joints
Implementation Method 2
Due to the use of materials in the packages with different coefficients of thermal expansion (CTE), including semiconductor substrates, package substrates, solder and mold compound, the materials expand and contract at different rates
Data Source
AI summary
In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.


