Flip Chip Substrate Fabrication via Carrier Removal
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Solution Overview
Problem
Conventional flip chip substrate manufacturing processes result in low integration, multiple layers, long leads, and high resistance, limiting their applicability to high-frequency semiconductor packaging due to complexity and high costs.
Innovation Solution
A method involving a carrier with sequential formation of resist, metal, and solder mask layers, followed by removal of the carrier and formation of solder bumps on conductive pads, which allows for increased integration and miniaturization without plated through holes, using etching-stop layers like iron or gold to streamline the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-layer substrate fabrication with plated through holes is used, then electrical connection is achieved, but substrate thickness increases and integration is reduced
Solution Approach 1:
The patent removes the carrier substrate from the final product structure, extracting only the necessary circuit patterns and conductive layers. This eliminates the need for plated through holes and reduces overall substrate thickness while maintaining electrical connection functionality through surface-mounted conductive layers.
Solution Approach 2:
The patent transitions from three-dimensional plated through holes penetrating the substrate to two-dimensional surface-mounted conductive layers. By moving electrical connections to the surface plane rather than through the thickness dimension, the substrate can be made thinner while maintaining integration.
2Adaptability or versatility
If multiple circuit build up processes are used to create multi-layer substrate, then circuit connections are expanded, but process complexity increases
Solution Approach 1:
The patent combines multiple circuit build-up operations into a single integrated process flow on the carrier. By forming all conductive layers, insulating layers, and circuit patterns while the carrier provides structural support, the process avoids the complexity of stacking and aligning multiple separate substrate layers.
Solution Approach 2:
The carrier substrate is used preliminarily to provide a stable foundation for forming all circuit structures. The carrier enables precise positioning and formation of conductive layers before final release, simplifying the overall process by providing a temporary but essential manufacturing platform.
3Reliability
If plated through holes are used for electrical connection, then connection interfaces are provided, but manufacturing cost increases
Solution Approach 1:
The carrier substrate serves as a disposable, low-cost temporary platform that enables precise manufacturing of the final thin substrate. The carrier is removed after serving its manufacturing purpose, having enabled cost-effective formation of conductive layers without requiring expensive plated through-hole processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances circuit integration, reduces substrate thickness, and simplifies the manufacturing process, addressing the limitations of conventional methods by improving integration and reducing complexity and cost.
Implementation Method 1
remove the resist layer, thereby exposing the second metal layer in the second openings of the first solder mask as the electrically conductive pads of the other side
Implementation Method 2
a first metal layer, an etching-stop layer, and a second metal layer are formed by electroplating or electroless plating
Implementation Method 3
a first metal layer, an etching-stop layer, and a second metal layer are formed by electroplating or electroless plating
Implementation Method 4
Finally, plural solder bumps are formed on the electrically conductive pads on both sides of the circuit build up structure
Data Source
AI summary
The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.