Flip-Chip Wafer-Level Package With Through Encapsulant Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging integrated circuits (ICs) to make them smaller, faster, and more reliable, while existing methods like flip-chip wire-bond packages and Through Silicon Vias (TSVs) are limited by cost and supply chain issues, and there is a need for more efficient electrical connections and reduced thermo-mechanical stresses.
Innovation Solution
The implementation of a flip-chip wafer-level package with a first die coupled to a flip-chip substrate, a second die stacked on the first die, an encapsulation compound, through encapsulant vias (TEVs) for electrical connections, and a redistribution layer to connect contacts on the second die to the TEVs, allowing for a package-on-package (PoP) configuration with reduced size and increased performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through Silicon Vias (TSVs) are used for electrical connections, then electrical connection efficiency is improved, but manufacturing cost and supply chain complexity increase
Solution Approach 1:
The patent extracts the via formation from the silicon substrate and relocates it to the encapsulant material. Through encapsulant vias (TEVs) are formed after encapsulation, allowing electrical connections to be made through the encapsulant rather than requiring complex TSV formation through the silicon die, thereby reducing manufacturing cost and supply chain complexity while maintaining electrical connection efficiency.
Solution Approach 2:
The patent performs preliminary encapsulation of the flip-chip component before forming the electrical vias. The encapsulation compound is applied and cured to enclose the first die, second die, and flip-chip substrate, and only after this encapsulation is complete are the TEVs formed. This preliminary action simplifies the overall manufacturing process by eliminating the need for complex TSV formation in silicon.
2Volume of moving object
If multiple dies are stacked to reduce package size, then volume is reduced, but assembly complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple functional components into a single integrated package structure. The first die, second die, flip-chip substrate, and encapsulation compound are combined into one unified package with external electrical connections provided through the encapsulant. This merging approach reduces the overall package volume while managing assembly complexity through a standardized package structure.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacking by placing the second die on top of the first die in a vertical arrangement. This dimensional change allows multiple dies to be integrated within a smaller footprint volume, achieving miniaturization while the encapsulation and TEV structure provides a standardized interface that manages the complexity of the three-dimensional assembly.
3Ease of manufacture
If flip-chip wire-bond packaging is used, then manufacturing is simplified, but electrical connection performance and speed are limited
Solution Approach 1:
The patent replaces the mechanical wire-bonding system with a direct electrical connection system using conductive vias. Instead of using wire bonds to connect electrical contacts between dies, the invention uses through encapsulant vias filled with conductive material to provide direct electrical pathways, eliminating the mechanical wire-bonding step while improving electrical connection speed and performance.
Data Source
AI summary
An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.