Flip-Chip Interconnection Using Thick Conductive Pads
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Solution Overview
Problem
The flip chip interconnection technique faces challenges such as high temperature degradation, parasitic capacitances and dielectric losses from underfill, and sensitivity to thermomechanical stresses, which are exacerbated by the banning of lead in solder alloys and limitations in interconnection height and density, especially for fragile chips and irregular patterns.
Innovation Solution
The method involves producing and bonding thick conductive layers by etching and using conductive glue to create interconnection pads with high aspect ratios, allowing for low-temperature assembly without underfill, and using epoxy resins with conductive fillers to manage thermomechanical stresses and achieve high interconnection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature is applied to melt solder balls for interconnection, then reliable electrical connection is achieved, but degradation of fragile electronic chips occurs
Solution Approach 1:
The patent changes the temperature parameter from high (solder reflow >200°C) to low (conductive glue curing <100°C), enabling interconnection of temperature-sensitive chips without degradation while maintaining connection reliability through the conductive glue's adhesive and conductive properties
Solution Approach 2:
The patent replaces expensive, temperature-sensitive solder ball interconnection with a more robust conductive glue approach that tolerates low temperatures, sacrificing the high-temperature soldering process for chip-friendly low-temperature curing
2Strength
If underfill is applied to consolidate the assembly, then mechanical strength is improved, but parasitic capacitances and dielectric losses are introduced
Solution Approach 1:
The patent extracts and removes the underfill step from the interconnection process entirely, relying instead on the conductive glue's inherent adhesive properties and the thick pad design to provide mechanical strength without introducing parasitic capacitances or dielectric losses
3Temperature
If serigraphic deposition of conductive glue is used, then low temperature processing is achieved, but interconnection density is reduced due to large pad surface area requirements
Solution Approach 1:
The patent transitions from two-dimensional serigraphic deposition to three-dimensional thick pad structures with aspect ratios ≥0.5, enabling low-temperature processing while achieving high interconnection density through vertical dimension exploitation
4Area of moving object
If lithography is used to manufacture conductive epoxy resin pads, then large form factor pads are produced, but pad height is limited to approximately 16 μm
Solution Approach 1:
The patent inverts the conventional approach by first creating thick conductive layers (≥100 μm) through deposition, then patterning them to form pads, rather than trying to build height through lithography alone, thereby achieving both large surface area and significant height
5Reliability
If thick conductive pads are used to limit thermomechanical stresses, then stress resistance is improved, but interconnection density is reduced due to large pad surface area
Solution Approach 1:
The patent uses conductive glue as a flexible, compliant material that can accommodate thermomechanical stress through its viscoelastic properties, allowing thick pads to provide stress resistance without requiring excessive surface area, thus maintaining high interconnection density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces thermomechanical stresses, enables interconnection of components with diverse thermal expansion coefficients, and allows for high-density, low-temperature assembly of components with complex interconnection patterns, suitable for sensitive chips like CdTe sensors, while avoiding lead and underfill-related issues.
Implementation Method 1
bonding, by means of at least one conductive adhesive, to a surface of an electronic component or of a substrate
Implementation Method 2
a step of hardening (in particular by polymerization or crosslinking) of said or at least one said conductive adhesive at a temperature less than or equal to 40°C
Implementation Method 3
the production of at least one interconnection pad, in correspondence of said or each pad or reception area to be connected, by etching of said thick layer
Implementation Method 4
Said or each conductive glue can be an epoxy resin containing a conductive filler
Implementation Method 5
Said or at least one said interconnection pad may have a height at least equal to half of the smallest of its lateral dimensions, that is to say an aspect ratio greater than or equal to 0.5
Data Source
AI summary
The invention relates to a process for flip-chip connection of an electronic component (D) to a substrate (B), characterized in that it comprises producing at least one interconnect pad (PC) by etching a thick conductive film and bonding it, by means of at least one conductive adhesive, between a receiving pad or area of said electronic component and a receiving pad or area (PAS) of said substrate.