Flip Chip Underfill Void Prevention via Insulating Film Opening
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Solution Overview
Problem
In semiconductor devices with flip chip connections, voids often form in the underfill layer due to air being trapped during the filling process, leading to reliability issues such as cracks, especially during the reflow step.
Innovation Solution
The insulating film, such as a solder resist, is designed with an opening larger than the semiconductor chip, ensuring the chip fits entirely within the opening when viewed vertically, preventing level differences and air entrapment, and an underfill layer is used to seal the gap between the chip and the solid state device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the insulating film opening is smaller than the semiconductor chip, then the chip is properly positioned, but air is trapped during underfill material injection causing void formation
Solution Approach 1:
The patent inverts the conventional approach by making the insulating film opening larger than the chip rather than smaller. This reversal eliminates the air trapping problem that occurs when the opening is smaller, while the chip positioning is maintained through other means such as alignment marks or bonding precision.
Solution Approach 2:
The patent segments the opening into two functional zones: a first opening for underfill material injection that is larger than the chip to prevent air entrapment, and a second opening (or patterned region) that is smaller than the chip to maintain proper chip positioning and alignment during bonding.
2Reliability
If the opening is larger than the chip, then air entrapment is prevented, but the level difference between inside and outside of opening increases
Solution Approach 1:
The patent applies local quality by creating different opening sizes in different regions of the insulating film. The first opening (or first patterned region) is larger than the chip to prevent air entrapment during underfill injection, while the second opening (or second patterned region) is smaller to maintain proper level difference geometry for chip positioning.
3Shape
If the opening is smaller than the chip, then level difference is minimized, but voids form in the underfill layer during filling
Solution Approach 1:
The patent inverts the conventional approach by making at least part of the insulating film opening larger than the chip. This reversal specifically addresses the void formation problem by ensuring adequate space for underfill material to flow in without trapping air, even though it increases the level difference in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents void formation in the underfill layer, enhancing the reliability of the semiconductor device by eliminating air entrapment and potential cracks, thereby improving the bonding process and device stability.
Implementation Method 1
Capillarity causes the underfill material 57P to enter and spread between the surface of the solder resist film 56 and the functional surface 53a of the semiconductor chip 53
Data Source
AI summary
A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.