Flip Chip Semiconductor Device Via Electrode Thin Profile

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Solution Overview

Problem

Existing flip chip power semiconductor devices with vertical conduction typically have electrodes on opposite sides of the die, making it difficult to achieve a thin device configuration with all electrodes on the same surface, which limits cost advantages and performance.

Innovation Solution

A semiconductor die with a via extending through its entire thickness, where a via electrode connects a top power electrode to a bottom power electrode, allowing for a thin vertical conduction flip chip MOSFET with all electrodes on the same surface, fabricated by etching a trench, adding a metal via electrode, and grinding to expose the trench at the bottom surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If electrodes are disposed on opposite sides of the die (vertical conduction), then current path efficiency is improved, but device thickness cannot be reduced below 200 microns and all electrodes cannot be on the same surface

Engineering Contradiction:
Improvecurrent path efficiencyVSAvoiddevice thickness
Core Design Contradiction:
Ease of operationVSLength of moving object

Solution Approach 1:

The patent transitions from a planar electrode arrangement to a three-dimensional via structure. By etching trenches through the die thickness and filling them with conductive material, the invention creates vertical interconnects that enable all power electrodes to be positioned on the same surface while maintaining efficient current paths through the via electrodes, thus resolving the contradiction between thin profile and effective current conduction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The via electrodes are nested within the die structure itself, with trenches etched into the die and filled with conductive material. This nesting approach allows the current path to be embedded within the die thickness, enabling thin device configuration while maintaining efficient vertical conduction paths from top to bottom surfaces.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If device thickness is reduced to less than 200 microns, then cost advantage and low resistivity are improved, but it becomes difficult to achieve all electrodes on the same surface

Engineering Contradiction:
Improvecost advantageVSAvoidelectrode configuration
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent segments the electrode configuration into two functional groups: power electrodes all positioned on the top surface for simplified mounting, and signal electrodes on the bottom surface. The via electrodes segment the vertical conduction path into discrete trenches filled with conductive material, enabling thin device thickness while maintaining functional separation and simplifying the overall mounting process.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If all power electrodes are positioned on the same surface, then mounting simplicity and cost efficiency are improved, but vertical conduction paths become more complex to implement

Engineering Contradiction:
Improvemounting simplicityVSAvoidvia structure complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The via electrodes are formed by etching trenches directly into the die and filling them with conductive material during the manufacturing process. This self-integrated approach creates the vertical conduction paths as an inherent part of the die structure, eliminating the need for separate complex interconnect structures and simplifying the overall device assembly while maintaining all power electrodes on the same surface.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8154105B2Flip chip semiconductor device and process of its manufacture
Publication Date: 2012.04.10 INFINEON TECHNOLOGIES AMERICAS CORP
  • US8154105B2 patent drawing
  • US8154105B2 patent drawing
  • US8154105B2 patent drawing

AI summary

A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a bottom surface of the die.