Flip Chip Package Laminate Structure for Warpage Control
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Solution Overview
Problem
Semiconductor flip chip packages experience warpage due to thermal expansion differences between chip and substrate materials, leading to stress and potential cracking, especially in large chip sizes, which affects reliability and co-planarity.
Innovation Solution
A semiconductor chip package design incorporating a multi-layer laminate epoxy sheet with a gap between the chip and substrate, filled with epoxy layers of varying filler sizes, and optionally a stiffener ring for enhanced warpage control, replacing conventional underfilling processes and stiffeners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stiffener is used to constrain the substrate, then warpage prevention is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the stiffener component from the package structure entirely. Instead of adding a stiffener to constrain the substrate, the invention uses the substrate itself as the constraint element through recesses formed directly in the substrate that engage with protrusions on the chip package, thereby preventing warpage without additional components.
Solution Approach 2:
The patent integrates the warpage constraint function directly into the substrate structure by forming recesses within it. This merges the substrate's structural support function with the warpage prevention function, eliminating the need for a separate stiffener component and simplifying the overall package structure.
2Reliability
If a stiffener is added to prevent warpage, then thermal performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent eliminates the stiffener component entirely, removing the associated manufacturing costs of procuring, positioning, and bonding the stiffener to the substrate. The warpage prevention function is achieved through substrate recesses that are formed during substrate fabrication, which is already part of the manufacturing process.
Solution Approach 2:
The substrate is given multiple functions: it provides electrical connections, mechanical support, thermal management, and warpage constraint. By making the substrate multi-functional, the patent eliminates the need for separate components like stiffeners, thereby reducing manufacturing cost while maintaining thermal performance.
3Area of moving object
If the chip size is increased, then functionality is improved, but package warpage increases
Solution Approach 1:
The patent creates a balanced stress distribution by forming recesses in the substrate that engage with protrusions on the chip package. This configuration creates an equipotential stress state that compensates for the thermal expansion differences caused by large chip sizes, preventing warpage while maintaining the benefits of larger chip area.
4Reliability
If conventional underfilling is used, then stress distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The patent removes the underfill material and underfilling process from the manufacturing sequence. Instead of applying underfill material between the chip and substrate to distribute stress, the invention uses mechanically integrated protrusion-recess features that provide stress distribution through rigid structural engagement, eliminating the need for liquid underfill material and the complex dispensing and curing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer laminate epoxy sheet effectively reduces package warpage and enhances reliability by distributing stress evenly, while eliminating the need for complex molding processes and additional stiffeners, thus reducing costs.
Implementation Method 1
the package is highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate and chip materials
Data Source
AI summary
A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.