Flip-Flop Chain Reset for Memory Write Accuracy
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Solution Overview
Problem
The existing data write process in memory chips experiences lower accuracy due to repeated sampling of internal write commands caused by phase deviations between the clock signal and data strobe signal, leading to errors in data write operations.
Innovation Solution
A command processing circuit with a series of flip-flops is used to sample internal write commands, where the output of one flip-flop is connected to the input of the next, allowing for the selection of a target flip-flop to reset the start and end positions of the pulse, preventing repeated sampling by aligning the active level with the target time of the pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase deviation between clock signal and data strobe signal occurs, then sampling timing becomes misaligned, but repeated sampling of internal write commands occurs leading to data write errors
Solution Approach 1:
The patent applies preliminary action by using the first flip-flop to detect and mark the start position of the internal write command pulse before subsequent flip-flops process the signal. This advance detection prevents repeated sampling by establishing a reference point that synchronizes the sampling operation with the actual pulse timing, thereby resolving the contradiction between sampling accuracy and data write reliability
Solution Approach 2:
The patent implements feedback by using the output of each flip-flop as the input for the next flip-flop in the series, creating a chain where each stage's output feeds back into the processing sequence. This feedback mechanism ensures that sampling decisions are based on accumulated state information from previous stages, preventing erroneous repeated sampling and improving both measurement precision and reliability
Data Source
AI summary
Embodiments provide a command processing circuit and a data processing circuit, including a plurality of flip-flops. An output terminal of a former flip-flop is connected to an input terminal of a latter flip-flop. The flip-flop is configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, to sample data. An output terminal of a target flip-flop is connected to a target terminal of a first flip-flop, the target flip-flop is a flip-flop whose time of outputting an active level overlaps target time, where the target time is start time and/or end time of a pulse in the internal write command. The target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level.