Pulse-Triggered Flip-Flop Clear/Preset Without Output Short Circuits
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Solution Overview
Problem
Pulse-triggered flip-flop circuits in semiconductor integrated circuits face challenges in implementing clear and preset functions due to the risk of short circuits when using pull-down or pull-up circuits, which are not feasible in the same manner as in master-slave flip-flop circuits.
Innovation Solution
Incorporating a clear portion and logic circuits that perform logical operations between input data and clear or preset signals to control the state retention node, allowing for safe clearing and presetting of the node levels during specific transition periods, and using AND circuits to manage data input effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pull-down circuit or pull-up circuit is added to the output node of a pulse-triggered flip-flop circuit to clear or preset the output node, then clear and preset functions can be provided, but a short circuit can occur in the output node depending on the state of input data
Solution Approach 1:
The patent introduces logic circuits as intermediary components between the clear/preset signals and the state retention node. These logic circuits process the clear signal and input data together (e.g., using AND operations) before affecting the state retention node, thereby mediating the interaction to prevent direct conflicts that would cause short circuits while still enabling clear and preset functions
2Adaptability or versatility
If clear and preset functions are implemented in a pulse-triggered flip-flop circuit, then the circuit becomes more versatile, but the circuit complexity increases due to the need for additional logic circuits
Solution Approach 1:
The patent merges the clear function with the data input path by using logic circuits that combine the clear signal with input data signals. Instead of adding completely separate clear/preset circuitry, the clear function is integrated into the existing data input logic, thereby reducing overall circuit complexity while maintaining versatility
Data Source
AI summary
In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.