Flip-Flop Clock Control for Quiescent Switching Power Reduction
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Solution Overview
Problem
Conventional flip-flop electronic circuits dissipate significant power due to clocking even when they are quiescent, leading to increased power consumption, heat generation, and reduced reliability, as they receive clock signals during inactive periods.
Innovation Solution
Implementing a clock control circuit that compares the input to the master latch with the output of the slave latch to block the clock signal during quiescent conditions, reducing the number of gates receiving the clock signal and thereby minimizing switching capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional flip-flop circuit receives clock signals continuously, then the flip-flop can respond to state changes, but power consumption increases significantly during quiescent periods
Solution Approach 1:
The patent applies periodic action by enabling the clock signal to pass through the clock control circuit only during specific periods when state changes are detected. The clock control circuit compares the data input with the stored output and enables clocking only when they differ, creating a periodic rather than continuous clock signal delivery pattern that reduces power consumption during quiescent periods.
Solution Approach 2:
The clock control circuit serves as an intermediary between the continuous clock signal source and the flip-flop latches. It mediates the clock signal delivery by conditionally blocking or passing the clock based on state change detection, thereby preventing direct continuous clocking of the latches and reducing unnecessary power consumption.
2Use of energy by moving object
If clock signals are blocked during quiescent periods, then power consumption is reduced, but the flip-flop may fail to respond when state changes occur
Solution Approach 1:
The patent applies preliminary action by performing state change detection before enabling clock signal delivery. The clock control circuit continuously or periodically compares the data input with the stored output in advance, and only enables the clock signal when a state change is detected, ensuring the flip-flop responds reliably while minimizing unnecessary clocking.
Solution Approach 2:
The clock control circuit implements feedback by continuously monitoring the relationship between the data input and the stored output. This feedback mechanism ensures that the clock signal is enabled only when the comparison indicates a state change is needed, maintaining reliability while reducing power consumption during quiescent periods.
3Reliability
If multiple gates receive clock signals simultaneously, then the flip-flop operates correctly, but the total switching capacitance and power consumption increase
Solution Approach 1:
The patent applies the taking out principle by extracting or removing the clock signal from gates that do not need to switch during quiescent periods. The clock control circuit selectively blocks the clock signal from the master and slave latches when no state change is detected, reducing the total switching capacitance that must be charged and discharged with each clock cycle.
Data Source
AI summary
Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.