Flip-Flop State-Holding Circuit Without a Clock Buffer
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Solution Overview
Problem
Conventional flip-flop circuits require a clock buffer to generate a clock inverted signal, leading to increased power consumption, especially during low switching rates where the power consumption in the clock buffer is wasteful.
Innovation Solution
A semiconductor integrated circuit design that eliminates the need for a clock buffer by using a state-holding circuit with P-channel and N-channel field-effect transistors controlled by data signals and clock signals, allowing the circuit to hold states without an additional clock inverted signal generation, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock buffer is used to generate the clock inverted signal, then the flip-flop circuit can operate correctly, but the power consumption increases
Solution Approach 1:
The invention extracts and eliminates the clock buffer component from the conventional flip-flop circuit. By removing this power-consuming element and replacing it with transistors that directly utilize the clock signal, the circuit achieves correct operation without the additional power consumption associated with clock buffer operation.
Solution Approach 2:
The P-channel and N-channel transistors are designed to perform multiple functions: they act as switches controlled by the clock signal, generate the necessary inverted signals through their complementary operation, and enable state holding functionality. This multi-functionality eliminates the need for separate clock buffer circuits.
2Ease of operation
If a clock buffer operates at every clock transition, then the clock inverted signal is generated, but the power consumption increases especially at low switching rates
Solution Approach 1:
The circuit components themselves (P-channel and N-channel transistors) perform the signal inversion function that previously required a separate clock buffer. The transistors automatically generate the inverted clock signal through their inherent switching behavior when controlled by the clock signal, making the system self-sufficient and eliminating wasteful power consumption.
3Use of energy by moving object
If P-channel and N-channel transistors are used instead of a clock buffer, then power consumption is reduced, but the circuit structure becomes more complex
Solution Approach 1:
The invention merges the clock buffer functionality with the existing flip-flop circuit components. The P-channel and N-channel transistors are integrated into the state holding circuit structure, combining the clock signal distribution, inversion, and state control functions into a unified circuit architecture that reduces overall complexity despite adding transistor elements.
Data Source
AI summary
A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.