Single-Edge Flip-Flop Layout to Cut Clock Parasitic Capacitance
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Solution Overview
Problem
Current flip-flop circuits in digital synchronous systems contribute significantly to clocking power, with parasitic capacitance becoming a major portion of power dissipation, especially below the 7 nm process technology node, limiting further power savings and requiring new circuit innovations to reduce clocking power.
Innovation Solution
A parasitic-aware single-edge triggered flip-flop design that optimizes layout through process-circuit co-optimization, eliminating metal routes and diffusion notches, and utilizing scaling boosters like contact-over-active gate (COAG) to minimize parasitic capacitance, thereby reducing clock power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If process technology is scaled down below 7 nm to improve energy efficiency, then device size is reduced, but parasitic capacitance increases limiting further power savings
Solution Approach 1:
The patent extracts and eliminates the harmful metal routes connecting diffusion regions in the flip-flop layout. By removing these metal interconnects and replacing them with direct diffusion-to-diffusion contacts, the parasitic capacitance from metal routing is extracted from the system, directly reducing the harmful parasitic capacitance while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from planar metal-route-based connectivity to a vertical/diffusion-based connectivity approach. By using diffusion notches and direct diffusion contacts instead of metal layers for interconnection, the design moves away from the traditional planar metal routing dimension, reducing parasitic capacitance in the critical clocking paths.
2Area of stationary object
If minimum sized devices are used to reduce area, then device footprint is minimized, but parasitic capacitance contribution increases
Solution Approach 1:
The patent applies different layout qualities to different regions of the flip-flop. Specifically, the clocking paths use optimized diffusion-to-diffusion contacts with minimized parasitic capacitance, while other regions can use standard minimum-sized devices. This local optimization of the clocking network reduces parasitic capacitance in the most critical paths without requiring overall device downsizing.
3Productivity
If deeper pipelines are implemented to increase frequency, then processing throughput is improved, but clocking power increases
Solution Approach 1:
The patent merges the clock and data diffusion regions in the flip-flop layout, allowing shared diffusion structures to serve both clocking and data paths. By combining these functions and eliminating redundant metal routes, the parasitic capacitance is reduced, enabling lower power operation even with deeper pipelines that require more flip-flops.
Data Source
AI summary
A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.