Multi-Phase Flip-Flop Divider for Accurate Clock Phase Distribution
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Solution Overview
Problem
Conventional clock frequency dividers generate output clocks with phase errors when connected in series, leading to inaccuracies in modulation/demodulation of data signals due to non-identical load conditions of output ends.
Innovation Solution
A frequency dividing circuit utilizing two flip-flops with four clock signals of different phases, ensuring identical load conditions and accurate phase distribution of output clocks, which are controlled by complementary clock signals to maintain phase accuracy across stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two conventional frequency dividers are coupled in series to perform divide-by-four calculation, then frequency division function is achieved, but phase errors occur due to non-identical load conditions of output ends
Solution Approach 1:
The patent applies asymmetry by changing the connection topology from series to parallel configuration. Instead of connecting frequency dividers in series where output of one feeds input of another (creating unequal load conditions), the invention connects multiple frequency dividers in parallel to a common input, ensuring each divider operates under identical load conditions. This asymmetric topological change resolves the phase accuracy issue while maintaining frequency division functionality.
2Productivity
If conventional frequency dividers are connected in series, then frequency division is achieved, but load conditions of output ends are not identical causing phase errors
Solution Approach 1:
The patent inverts the conventional series connection approach by implementing a parallel connection architecture. Rather than having dividers chain sequentially (output of divider 1 → input of divider 2), the invention reverses this by having all dividers receive the same input simultaneously and distribute outputs to multiple destinations. This inversion of connection topology ensures identical load conditions and maintains phase consistency across all output channels.
3Adaptability or versatility
If four output clocks are generated with 90-degree phase differences, then quadrature clock signals are produced, but phase errors propagate when used in modulation circuits
Solution Approach 1:
The patent applies universality by designing a frequency divider architecture that simultaneously serves multiple functions: it generates quadrature clock signals (0°, 90°, 180°, 270° phases) while maintaining identical load conditions for all outputs. The parallel connection structure enables the system to provide both the adaptability of quadrature signal generation and the precision required for modulation circuits, making the divider universally applicable to various clocking requirements without phase errors.
Data Source
AI summary
Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.