Flip-Flop Clock Phasing for Low-Voltage Data Stability
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Solution Overview
Problem
Flip-flop circuits are limited by minimum operating voltage and energy dissipation, leading to incorrect data storage at voltages below the minimum operating voltage, and suffer from signal conflicts and jitters.
Innovation Solution
The proposed flip-flop design incorporates phase shift circuits and feedback circuits controlled by advanced clock signals to prevent signal conflicts and jitters, allowing operation at lower voltages by improving the minimum operating voltage (Vmin) by 25-50 mV.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional flip-flop circuits are operated at lower voltages, then power consumption is reduced, but data storage becomes incorrect and unreliable
Solution Approach 1:
The patent applies preliminary action by pre-charging nodes and pre-positioning transistors in specific states before the actual data storage operation. The flip-flop circuit prepares its internal nodes (such as precharging nodes to specific voltage levels) in advance, allowing it to reliably capture and store data even at reduced operating voltages. This preliminary preparation ensures that the circuit is in an optimal state to withstand lower voltage conditions without compromising data integrity.
2Device complexity
If conventional flip-flop circuits use traditional clocking schemes, then circuit simplicity is maintained, but signal conflicts and jitters occur
Solution Approach 1:
The patent segments the clocking function into multiple independent phases (first clock signal and second clock signal) that are applied to different parts of the flip-flop circuit at different times. This segmentation prevents signal conflicts by ensuring that clock edges do not simultaneously affect multiple critical nodes. The divided clocking approach eliminates jitter while maintaining overall circuit simplicity through systematic phase distribution.
Solution Approach 2:
The patent employs periodic action through multi-phased clocking schemes where clock signals are applied in distinct time periods and phases. The first and second clock signals operate in alternating or coordinated periodic cycles, allowing the flip-flop to process data through different stages (such as master latch phase and slave latch phase) without signal interference. This periodic segmentation of clocking operations ensures stable signal transitions.
3Ease of manufacture
If conventional flip-flop circuits use standard designs, then ease of manufacture is maintained, but minimum operating voltage remains high
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics of transistors within the flip-flop circuit, such as adjusting threshold voltages, channel widths, and lengths of specific transistors to optimize low-voltage operation. These parameter adjustments enable the circuit to function reliably at lower minimum operating voltages while maintaining compatibility with standard manufacturing processes. The design tweaks transistor parameters to enhance voltage efficiency without requiring complete redesign of the manufacturing approach.
Data Source
AI summary
A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.