Flip-Flop Clock Routing Layout for Master-Slave Delay Tuning
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in optimizing the time delays within flip-flop circuits, particularly in achieving a higher time delay from the clock circuit to the master latch circuit compared to the slave latch circuit, which limits the flop speed and overall performance.
Innovation Solution
The IC layout is redesigned to physically arrange the master latch circuit, slave latch circuit, and clock circuit in a specific configuration, with longer routing paths from the clock circuit to the master latch circuit than to the slave latch circuit, thereby increasing the time delay to the master latch circuit relative to the slave latch circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the routing path from the clock circuit to the master latch circuit is made longer than to the slave latch circuit, then the time delay to the master latch circuit increases, but the layout complexity and routing complexity increase
Solution Approach 1:
The patent applies asymmetry by intentionally creating unequal routing path lengths from the clock circuit to the master latch circuit versus the slave latch circuit. The clock circuit is positioned and routed such that the path to the master latch circuit is deliberately longer, establishing asymmetric time delays that enable the master latch to capture data after the slave latch has already been updated, thereby increasing flop speed without adding complex control logic
Solution Approach 2:
The patent utilizes spatial arrangement in the layout to achieve the desired time delay differentiation. By strategically positioning the clock circuit, master latch circuit, and slave latch circuit in specific locations and using multi-layer routing, the patent creates path length differences in the physical layout domain, translating spatial relationships into temporal delays without increasing functional complexity
2Speed
If the routing path from the clock circuit to the master latch circuit is made longer than to the slave latch circuit, then the flop speed increases, but the routing complexity increases
Solution Approach 1:
The patent applies asymmetry by intentionally creating unequal routing path lengths from the clock circuit to the master latch circuit versus the slave latch circuit. The clock circuit is positioned and routed such that the path to the master latch circuit is deliberately longer, establishing asymmetric time delays that enable the master latch to capture data after the slave latch has already been updated, thereby increasing flop speed without adding complex control logic
Solution Approach 2:
The routing structure serves itself by using the inherent propagation delay differences created by the asymmetric path lengths. The longer path to the master latch automatically provides the necessary timing separation without requiring additional delay elements, control signals, or complex timing management circuitry, allowing the routing infrastructure to accomplish the timing function inherently
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) device includes: performing front-end-of-line (FEOL) processing to fabricate a plurality of transistors over a substrate, and performing back-end-of-line (BEOL) processing to fabricate a redistribution structure electrically coupling the plurality of transistors into a master latch circuit, a slave latch circuit, and a clock circuit. The redistribution structure includes: a first electrical connection electrically coupling the clock circuit to the master latch circuit, and a second electrical connection electrically coupling the clock circuit to the slave latch circuit. The first electrical connection is physically longer than the second electrical connection.