Master-Slave Flip-Flop Clock Skew for Lower Propagation Delay
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Solution Overview
Problem
Conventional master-slave flip-flops face challenges in meeting the short propagation delay specifications required for high-speed memory systems, such as DDR2/3 DRAM devices, as they are difficult to achieve with traditional complementary clocking schemes.
Innovation Solution
A clocking scheme is introduced where the slave latch is made transparent earlier by skewing the clock signal CKS with respect to CKM, using a clock buffer to derive and toggle these signals from an input clock, thereby reducing the propagation delay and preserving set-up time by ensuring both latches are not simultaneously transparent.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional complementary clocking scheme is used in master-slave flip-flop, then the latches are properly controlled to avoid simultaneous transparency, but the propagation delay is too long to meet high-speed memory specifications
Solution Approach 1:
The patent applies asymmetry by skewing the clock signal CKS to the slave latch relative to the clock signal to the master latch. This creates an asymmetric timing relationship where the slave latch is enabled earlier than in conventional symmetric complementary clocking, thereby reducing propagation delay while maintaining proper master-slave operation through controlled transparency periods.
Solution Approach 2:
The patent implements preliminary action by enabling the slave latch to become transparent before the master latch completes its operation. The skewed clocking arrangement allows the slave latch to be prepared in advance, reducing the overall propagation delay from the input clock to the output while ensuring data stability through maintained set-up time margins.
2Loss of time
If clock signals are skewed to reduce propagation delay, then the slave latch becomes transparent earlier, but there is a risk that both latches may become simultaneously transparent
Solution Approach 1:
The patent applies partial action by implementing a controlled period where both latches are temporarily transparent due to clock skew, but limiting this condition to a brief interval. This partial simultaneous transparency is sufficient to reduce propagation delay while the overall timing design ensures data stability and prevents harmful race conditions through maintained set-up time margins.
Data Source
AI summary
A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.