Flip-Flop Counter Circuit for Switchable Protection Delay Times
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Solution Overview
Problem
Existing battery protection ICs require complex circuit configurations and suffer from reduced detection accuracy due to the need for a check circuit to adjust delay times for overcharge, overdischarge, and overcurrent detection, which complicates the manufacturing process.
Innovation Solution
A counter circuit comprising multiple stages of trigger-type flip flops connected in cascade, where each stage receives a mode signal to adjust the frequency or allow passage of the input signal, enabling simple switching between normal and shortened delay modes without altering charge current to the condenser.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a check circuit is added to switch delay times by changing charge current to the condenser, then the delay time can be adjusted between normal, shortened, and no-delay modes, but the circuit configuration becomes complex and the detection accuracy is lowered
Solution Approach 1:
The patent changes the operational parameter of the flip-flop circuit by introducing a mode signal that switches between normal operation mode and direct passage mode. This allows the delay time to be adjusted without changing the physical circuit structure or adding complex check circuits, thereby resolving the contradiction between adaptability and device complexity
Solution Approach 2:
The patent divides the delay function into multiple flip-flop stages that can be selectively activated. By using a mode signal to control which stages are active, the circuit achieves variable delay times without requiring a complex check circuit, thus reducing overall circuit complexity while maintaining adaptability
2Adaptability or versatility
If a check circuit is added to switch delay times, then the delay time can be adjusted, but the detection accuracy of overcharge and overdischarge circuits is lowered
Solution Approach 1:
The patent uses a mode signal to change the operational parameter of the flip-flop circuit, switching between normal delay operation and direct passage mode. This parameter change approach allows delay time adjustment without introducing the charge current changes that would affect detection accuracy, thereby resolving the contradiction between adaptability and measurement precision
3Loss of time
If the delay time is shortened or eliminated for testing, then the testing time is reduced, but a complex check circuit with multiple gates and inverters is required
Solution Approach 1:
The patent introduces a mode signal parameter that can be set to different values (normal mode or test mode) to change the circuit's behavior. In test mode, the mode signal causes the flip-flop circuit to pass signals directly without delay, eliminating the need for complex check circuits while reducing testing time
Data Source
AI summary
A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode.