Master-Slave Flip-Flop Disturbance Detection for Data Integrity
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Solution Overview
Problem
Existing electronic circuits with synchronous flip-flops face challenges in detecting accidental or intentional disturbances, particularly in sensitive data handling applications, where dynamic and static effects can cause errors and unauthorized access, and there is a need for selective activation and deactivation of protection mechanisms.
Innovation Solution
A method for detecting disturbances in master-slave synchronous flip-flops involves cyclic control of bistable circuits through four successive periods, using interlocked and locked states to identify potential disturbances, with a logic circuit comparing input and output levels to generate validation signals for dynamic or static disturbances, and allowing for selective activation and deactivation of detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If disturbance detection is implemented in synchronous flip-flops, then reliability is improved, but device complexity increases
Solution Approach 1:
The disturbance detection mechanism is nested within the existing master-slave flip-flop structure. The validation logic is integrated into the feedback path between the master and slave bistable circuits, allowing detection functionality to be embedded without adding separate external detection circuits. This nesting approach enables disturbance detection while minimizing additional circuit complexity.
Solution Approach 2:
The flip-flop circuit performs self-validation by comparing its own internal states. The validation logic uses the existing Q and NQ outputs along with the intermediate signal from the master stage to detect disturbances, allowing the circuit to monitor itself without requiring external detection equipment. This self-service mechanism improves reliability while avoiding the complexity of external monitoring systems.
2Reliability
If continuous disturbance detection is activated, then reliability is improved, but use of energy increases
Solution Approach 1:
The disturbance detection is activated periodically rather than continuously. The validation logic is enabled during specific phases of the clock cycle, particularly during the transition periods when disturbances are most likely to occur. By gating the validation logic with clock signals and control logic, the system performs detection only when necessary, reducing power consumption while maintaining effective disturbance detection capability.
3Measurement precision
If detection periods are extended, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The validation logic quickly evaluates the critical comparison conditions during brief validation windows within the clock cycle. Rather than extending detection over long periods, the system rapidly checks the essential conditions (Q output matching expected state, intermediate signal validity) during specific high-probability disturbance windows. This rushing through the essential validation checks achieves sufficient detection accuracy without significant time loss.
Data Source
Figure 1~3
Figure 4A~4J
Figure 5~7
AI summary
The method involves triggering transparent latch type bistable circuits (11, 12) of a master-slave synchronous flip-flop (3) by output signals that are different from one another. A level of an intermediate connection point (35) between the bistable circuits is simultaneously compared with levels of validation signals (V1, V2) at respective input and output of the flip-flop, to provide an indication about presence of an eventual interference. An independent claim is also included for a master-slave synchronous flip-flop comprising logic circuits.