Flip-Flop Pixel Driving Circuit With Adjustable Clock Duty Cycle
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Solution Overview
Problem
The existing Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) driving modes for display technologies suffer from high power consumption, heat generation, and increased circuit complexity, which hinder advancements such as high PPI and narrow borders, while also failing to achieve low grey scale display effectively.
Innovation Solution
A flip-flop circuit with an AND gate, input control sub-circuit, duty cycle adjustment sub-circuit, and reset sub-circuit, capable of adjusting the duty cycle of clock signals to control the brightness of a driving transistor, thereby optimizing power usage and reducing heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If PWM driving mode is introduced to solve PAM's high power consumption and heat generation, then power consumption and heat are reduced, but circuit complexity increases significantly
Solution Approach 1:
The pixel driving circuit is divided into multiple sub-circuits: a first sub-circuit generates a first clock signal with 50% duty cycle, a second sub-circuit generates a second clock signal with adjustable duty cycle, and a third sub-circuit combines these signals. This segmentation allows independent optimization of each sub-circuit's function, reducing overall circuit complexity while achieving PWM-driven power savings and heat reduction.
Solution Approach 2:
The driving circuit is designed to support both PAM and PWM driving modes through a unified architecture. The circuit can operate in PAM mode for high brightness levels and switch to PWM mode for low brightness levels, making the system multi-functional and adaptable to different display requirements without requiring separate dedicated circuits for each mode.
2Adaptability or versatility
If PWM driving mode is introduced to achieve low grey scale display, then low grey scale display capability is improved, but circuit complexity increases
Solution Approach 1:
The circuit employs dynamic duty cycle adjustment in the second sub-circuit to achieve different grey scale levels. By dynamically varying the duty cycle of the second clock signal based on display requirements, the circuit can precisely control low grey scale levels without requiring complex additional circuitry, thus improving adaptability while keeping circuit complexity manageable.
Solution Approach 2:
A third sub-circuit acts as an intermediary to combine the first clock signal (50% duty cycle) and the second clock signal (adjustable duty cycle) to produce the final driving signal. This intermediary circuit simplifies the overall design by handling the signal combination logic in a dedicated module, reducing the complexity burden on other parts of the system while enabling precise low grey scale control.
3Ease of operation
If full-screen driving mode with fixed duty ratio is used, then driving simplicity is maintained, but power consumption remains high and heat generation is significant
Solution Approach 1:
The circuit changes the duty cycle parameter of the clock signals dynamically. The first sub-circuit generates a clock signal with fixed 50% duty cycle for simplicity, while the second sub-circuit generates a clock signal with variable duty cycle that can be adjusted according to display brightness requirements. This parameter variation enables PWM-based power saving and heat reduction while maintaining operational simplicity through standardized signal generation methods.
Data Source
AI summary
A flip-flop circuit and a pixel driving circuit are provided, and belong to the field of circuit technology. The flip-flop circuit includes: an AND gate having a first input terminal, a second input terminal, and an output terminal, the AND gate is configured to control the output terminal to output a clock signal based on potentials at the first input terminal and the second input terminal, and a potential of the clock signal jumps between a first power supply voltage and a second power supply voltage; an input control sub-circuit configured to transmit the first power supply voltage or the second power supply voltage to at least one of the first input terminal and the second input terminal in response to an input control signal; and a duty cycle adjustment sub-circuit configured to adjust a duty cycle of the clock signal in response to a data voltage control signal.